Datasheet AD9230-11 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter |
| Seiten / Seite | 29 / 3 — AD9230-11. TABLE OF CONTENTS. REVISION HISTORY. 10/08—Revision 0: Initial … |
| Dateiformat / Größe | PDF / 665 Kb |
| Dokumentensprache | Englisch |
AD9230-11. TABLE OF CONTENTS. REVISION HISTORY. 10/08—Revision 0: Initial Version
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AD9230-11 TABLE OF CONTENTS
Features .. 1 Theory of Operation .. 16 Applications ... 1 Analog Input and Voltage Reference ... 16 Functional Block Diagram .. 1 Clock Input Considerations .. 17 General Description ... 1 Power Dissipation and Power-Down Mode ... 18 Product Highlights ... 1 Digital Outputs ... 18 Revision History ... 2 Timing ... 19 Specifications ... 3 RBIAS ... 19 DC Specifications ... 3 Configuration Using the SPI ... 19 AC Specifications .. 4 Hardware Interface ... 20 Digital Specifications ... 5 Configuration Without the SPI .. 20 Switching Specifications .. 6 Memory Map .. 22 Timing Diagrams .. 7 Reading the Memory Map Table .. 22 Absolute Maximum Ratings .. 8 Reserved Locations .. 22 Thermal Resistance .. 8 Default Values ... 22 ESD Caution .. 8 Logic Levels ... 22 Pin Configurations and Function Descriptions ... 9 Transfer Register Map .. 22 Typical Performance Characteristics ... 13 Outline Dimensions ... 25 Equivalent Circuits ... 15 Ordering Guide .. 25
REVISION HISTORY 10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE
AD9230-11 TABLE OF CONTENTS
Features .. 1 Theory of Operation .. 16 Applications ... 1 Analog Input and Voltage Reference ... 16 Functional Block Diagram .. 1 Clock Input Considerations .. 17 General Description ... 1 Power Dissipation and Power-Down Mode ... 18 Product Highlights ... 1 Digital Outputs ... 18 Revision History ... 2 Timing ... 19 Specifications ... 3 RBIAS ... 19 DC Specifications ... 3 Configuration Using the SPI ... 19 AC Specifications .. 4 Hardware Interface ... 20 Digital Specifications ... 5 Configuration Without the SPI .. 20 Switching Specifications .. 6 Memory Map .. 22 Timing Diagrams .. 7 Reading the Memory Map Table .. 22 Absolute Maximum Ratings .. 8 Reserved Locations .. 22 Thermal Resistance .. 8 Default Values ... 22 ESD Caution .. 8 Logic Levels ... 22 Pin Configurations and Function Descriptions ... 9 Transfer Register Map .. 22 Typical Performance Characteristics ... 13 Outline Dimensions ... 25 Equivalent Circuits ... 15 Ordering Guide .. 25
REVISION HISTORY 10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE