Datasheet AD7262 (Analog Devices)

1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Data Sheet AD7262 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual simultaneous sampling 12-bit, 2-channel analog-to- AV V CC REFA digital converter (ADC) True differential analog inputs REF BUF AD7262 Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, 12-BIT ×24, ×32, ×48, ×64, ×96, ×128 VA+ SUCCESSIVE OUTPUT DOUTA PGA T/H APPROXIMATION DRIVERS Throughput rate per ADC VA– ADC 1 MSPS for AD7262 500 kSPS for AD7262-5 SCLK CAL Analog input impedance: >1 GΩ CS CONTROL REFSEL Wide input bandwidth LOGIC G0 −3 dB bandwidth: 1.7 MHz at gain = 2 G1 G2 4 on-chip comparators G3 SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 VDRIVE Device offset calibration, system gain calibration 12-BIT VB+ SUCCESSIVE OUTPUT PGA T/H DOUTB On-chip reference: 2.5 V V APPROXIMATION DRIVERS B– ADC PD0/D −40°C to +105°C operation IN PD1 BUF High speed serial interface PD2 SPI/QSPI™/MICROWIRE/DSP compatible VREFB 48-lead LFCSP and LQFP CA_CBVCC CA+ OUTPUT GENERAL DESCRIPTION COUTA C DRIVERS A– COMP C
The AD7262/AD7262-5 are dual, 12-bit, high speed, low power,
B+ OUTPUT COUTB C DRIVERS B–
successive approximation ADCs that operate from a single 5 V
COMP CA_CB_GND
power supply. The AD7262 features throughput rates of up to
CC_CDVCC
1 MSPS per on-chip ADC. The AD7262-5 features throughput
CC+ OUTPUT COUTC C DRIVERS
rates of up to 500 kSPS. Two complete ADC functions al ow
C– COMP CD+ OUTPUT
simultaneous sampling and conversion of two channels. Each
COUTD CD– DRIVERS COMP
ADC is preceded by a true differential analog input with a PGA.
CC_CD_GND
There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, 001 ×16, ×24, ×32, ×48, ×64, ×96, and ×128.
AGND DGND
07606- Figure 1. The AD7262/AD7262-5 contain four comparators. Comparator A and Comparator B are optimized for low power, while Compara-
PRODUCT HIGHLIGHTS
tor C and Comparator D have fast propagation delays. The AD7262/AD7262-5 feature a calibration function to remove any 1. Integrated PGA with a variety of flexible gain settings to device offset error and programmable gain adjust registers to allow al ow detection and conversion of low level analog signals. for input path (for example, sensor) offset and gain compensation. 2. Each PGA is fol owed by a dual simultaneous sampling The AD7262/AD7262-5 have an on-chip 2.5 V reference that ADC, featuring throughput rates of 1 MSPS per ADC for can be disabled if an external reference is preferred. the AD7262. The conversion results of both ADCs are simultaneously available on separate data lines or in succes- The AD7262/AD7262-5 are ideal y suited for monitoring smal sion on one data line if only one serial port is available. amplitude signals from a variety of sensors. They include all the 3. Four integrated comparators that can be used to count functionality needed for monitoring the position feedback signals signals from pole sensors in motor control applications. from a variety of analog encoders used in motor control systems. 4. Internal 2.5 V reference.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE