Datasheet AD7356 (Analog Devices) - 8

Data Sheet AD7356 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 INA+ 16 VDRIVE V 2 INA– 15 SCLK REF 3 A 14 SDATAA AD7356 REFGND 4 TOP VIEW 13 SDATAB (Not to Scale) AGND 5 12 DGND REF 6 B 11 AGND V 7 INB– 10 CS V 8
002
INB+ 9 VDD
06505- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 2 VINA+, VINA− Analog Inputs of ADC A. These analog inputs form a fully differential pair. 3, 6 REFA, REFB Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each reference pin with a 10 µF capacitor. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048 V + 100 mV to VDD. 4 REFGND Reference Ground. This is the ground reference point for the reference circuitry on the AD7356. Refer any external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. Connect the REFGND pin to the AGND plane of a system. 5, 11 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7356. All analog input signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7, 8 VINB−, VINB+ Analog Inputs of ADC B. These analog inputs form a fully differential pair. 9 VDD Power Supply Input. The VDD range for the AD7356 is 2.5 V ± 10%. Decouple the supply to AGND with a 0.1 µF capacitor in parallel with a 10 µF tantalum capacitor. 10 CS Chip Select. Active low logic input. This input provides the dual functions of initiating conversions on the AD7356 and framing the serial data transfer. 12 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7356. Connect this pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 13, 14 SDATAB, SDATAA Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. To access the 12 bits of data from the AD7356, 14 SCLK falling edges are required. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7356, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATAA or SDATAB, the data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB. 15 SCLK Serial Clock. Logic input. A serial clock input provides the serial clock for accessing the data from the AD7356. This clock is also used as the clock source for the conversion process. 16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. The voltage at this pin may be different than the voltage at VDD. The VDRIVE supply should be decoupled to DGND with a 0.1 µF capacitor in parallel with a 10 µF tantalum capacitor. Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair VOLTAGE REFERENCE ADC TRANSFER FUNCTION MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7356 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE