Datasheet AD9239 (Analog Devices) - 8

Data Sheet AD9239 TIMING DIAGRAM SAMPLE N N + 1 N – 40 ANALOG N – 39 INPUT SIGNAL N – 38 N – 37 SAMPLE RATE CLOCK SAMPLE ... ... RATE CLOCK SERIAL CODED SAMPLES: N – 40, N – 39, N – 38, N – 37 ... SERIAL ... ... ... ... ... ... DATA OUT DATA PACKET 1 (64 BITS)
002
8-BIT HEADER 48-BIT ADC 8-BIT ERROR CHANNEL ID DATA-WORD CORRECTION
06980- Figure 2. Timing Diagram
Table 5. Packet Protocol Bits[64:57] Bits[56:45] Bits[44:33] Bits[32:21] Bits[20:9] Bits[8:1]
Header Data 1 Data 2 Data 3 Data 4 ECC (8 bits MSB first) (12 bits MSB first) (12 bits MSB first) (12 bits MSB first) (12 bits MSB first) (8 bits MSB first) Rev. E | Page 7 of 40 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation Digital Start-Up Sequence Minimize Skew and Time Misalignment (Optional) Link Initialization (Required) Digital Outputs and Timing Digital Output Scrambler and Error Code Correction Error Correction Code Scramblers Inverter Balance Example Calculating the Parity Bits for the Hamming Code TEMPOUT Pin RBIAS Pin VCMx Pins RESET Pin PDWN Pin SDO Pin SDI/SDIO Pin SCLK Pin CSB Pin PGMx Pins Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide