Datasheet AD7625 (Analog Devices) - 6

Data Sheet AD7625 TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
Time Between Conversions1 tCYC 166 10,000 ns Acquisition Time tACQ 40 ns CNV± High Time tCNVH 10 40 ns CNV± to D± (MSB) Delay tMSB 145 ns CNV± to Last CLK± (LSB) Delay tCLKL 110 ns CLK± Period2 tCLK (tCYC − tMSB + tCLKL)/n 4 3.33 ns CLK± Frequency fCLK 250 300 MHz CLK± to DCO± Delay (Echoed-Clock Mode) tDCO 0 4 7 ns DCO± to D± Delay (Echoed-Clock Mode) tD 0 1 ns CLK± to D± Delay tCLKD 0 4 7 ns 1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. 2 For the minimum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) that are read. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18. Rev. B | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER INFORMATION TRANSFER FUNCTIONS ANALOG INPUTS TYPICAL CONNECTION DIAGRAM DRIVING THE AD7625 Differential Analog Input Source Single-Ended-to-Differential Driver VOLTAGE REFERENCE OPTIONS POWER SUPPLY Power-Up DIGITAL INTERFACE Conversion Control Echoed-Clock Interface Mode Self-Clocked Interface Mode APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING Exposed Pad VDD1 Supply Routing and Decoupling VIO Supply Decoupling Layout and Decoupling of Pin 25 to Pin 32 OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES