Datasheet AD7191 (Analog Devices)

Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors AD7191 FEATURES GENERAL DESCRIPTION Pin-programmable output rate
The AD7191 is a low noise, complete analog front end for high
Output data rate: 10 Hz, 50 Hz, 60 Hz, 120 Hz
precision measurement applications. It contains a low noise,
Pin-programmable PGA
24-bit sigma-delta (Σ-Δ) ADC. The on-chip low noise gain
Gain: 1, 8, 64, 128
stage means that signals of small amplitude can be interfaced
Pin-programmable power-down and reset
directly to the ADC. It contains two differential analog inputs.
RMS noise: 15 nV @ 10 Hz (gain = 128)
The part also includes a temperature sensor that can be used for
Up to 21.5 noise free bits (gain = 1)
temperature compensation.
Internal or external clock
For ease-of-use, all the features of the AD7191 are controlled by
Bridge power-down switch
dedicated pins. The on-chip PGA has a gain of 1, 8, 64, or 128,
Offset drift: 5 nV/°C
supporting a full-scale differential input of ±5 V, ±625 mV,
Gain drift: 1 ppm/°C
±78 mV, or ±39 mV. The output data rate can be programmed
Specified drift over time
to 10 Hz, 50 Hz, 60 Hz, or 120 Hz. Simultaneous 50 Hz and 60 Hz
Simultaneous 50 Hz/60 Hz rejection
rejection is obtained when the output data rate is set to 10 Hz
Internal temperature sensor
or 50 Hz; 60 Hz only rejection is obtained when the output data
Power supply: 3 V to 5.25 V
rate is set to 60 Hz. The AD7191 can be operated with the
Current: 4.35 mA
internal clock, or an external clock can be used.
Temperature range: –40°C to +105°C Package: 24-lead TSSOP
The part operates with a power supply of 3 V to 5.25 V. It consumes a current of 4.35 mA. It is available in a 24-lead
INTERFACE
TSSOP package.
2-wire serial SPI, QSPI™, and MICROWIRE™ compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gauge transducers Pressure measurement Medical and scientific instrumentation FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND REFIN(+) REFIN(–) AD7191 DOUT/RDY AIN1 SERIAL SCLK AIN2 Σ-Δ INTERFACE MUX PGA PDOWN AIN3 ADC AND CONTROL CHAN AIN4 LOGIC CLKSEL BPDSW PGA2 TEMPERATURE CLOCK SENSOR CIRCUITRY PGA1
01 0 3-
MCLK1 MCLK2 ODR2 ODR1 TEMP
16 08 Figure 1.
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Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN ANALOG INPUT CHANNELS TEMPERATURE SENSOR POWER-DOWN (PDOWN) CLOCK BIPOLAR CONFIGURATION DATA OUTPUT CODING BRIDGE POWER-DOWN SWITCH REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES EMI RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE