Datasheet AD9268 (Analog Devices) - 7

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AD9268 ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 2. AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz 25°C 79.7 78.9 78.8 dBFS fIN = 70 MHz 25°C 78.3 79.0 77.2 78.8 77.2 78.2 dBFS Full 78.0 77.1 76.5 dBFS fIN = 140 MHz 25°C 77.4 76.9 77.1 dBFS fIN = 200 MHz 25°C 75.5 75.0 75.5 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 2.4 MHz 25°C 79.4 78.3 78.3 dBFS fIN = 70 MHz 25°C 78.1 78.5 77.1 78.6 76.8 77.7 dBFS Full 77.7 76.8 76.2 dBFS fIN = 140 MHz 25°C 75.4 75.9 75.8 dBFS fIN = 200 MHz 25°C 74.3 72.2 74.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 12.9 12.7 12.7 Bits fIN = 70 MHz 25°C 12.8 12.7 12.6 Bits fIN = 140 MHz 25°C 12.2 12.3 12.3 Bits fIN = 200 MHz 25°C 12.0 11.7 12.0 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz 25°C −92 −87 −90 dBc fIN = 70 MHz 25°C −91 −88 −93 −87 −88 −85 dBc Full −87 −87 −84 dBc fIN = 140 MHz 25°C −80 −84 −83 dBc fIN = 200 MHz 25°C −82 −77 −79 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz 25°C 92 87 90 dBc fIN = 70 MHz 25°C 88 91 87 93 85 88 dBc Full 87 87 84 dBc fIN = 140 MHz 25°C 80 84 83 dBc fIN = 200 MHz 25°C 82 77 79 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN@ −23 dBFS) fIN = 2.4 MHz 25°C 93 100 88 dBFS fIN = 70 MHz 25°C 95 96 89 dBFS fIN = 140 MHz 25°C 98 96 90 dBFS fIN = 200 MHz 25°C 102 100 89 dBFS With On-Chip Dither (AIN @ −23 dBFS) fIN = 2.4 MHz 25°C 107 106 106 dBFS fIN = 70 MHz 25°C 107 109 106 dBFS fIN = 140 MHz 25°C 106 104 104 dBFS fIN = 200 MHz 25°C 104 108 105 dBFS Rev. A | Page 6 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE