Datasheet AD9269 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| Seiten / Seite | 41 / 3 — AD9269. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 8/2016—Rev. 0 to … |
| Revision | A |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
AD9269. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 8/2016—Rev. 0 to Rev. A. 1/2010—Revision 0: Initial Version
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AD9269 Data Sheet TABLE OF CONTENTS
Features .. 1 Clock Input Considerations .. 22 Applications ... 1 Power Dissipation and Standby Mode .. 24 Functional Block Diagram .. 1 Digital Outputs ... 25 Product Highlights ... 1 Timing ... 25 Revision History ... 2 Built-In Self-Test (BIST) and Output Test .. 26 General Description ... 3 Built-In Self-Test (BIST) .. 26 Specifications ... 4 Output Test Modes ... 26 DC Specifications ... 4 Channel/Chip Synchronization .. 27 AC Specifications .. 6 DC and Quadrature Error Correction (QEC) .. 28 Digital Specifications ... 7 Serial Port Interface (SPI) .. 29 Switching Specifications .. 8 Configuration Using the SPI ... 29 Timing Specifications .. 9 Hardware Interface ... 29 Absolute Maximum Ratings .. 10 Configuration Without the SPI .. 30 Thermal Characteristics .. 10 SPI Accessible Features .. 30 ESD Caution .. 10 Memory Map .. 31 Pin Configuration and Function Descriptions ... 11 Reading the Memory Map Register Table ... 31 Typical Performance Characteristics ... 13 Open Locations .. 31 AD9269-80 .. 13 Default Values ... 31 AD9269-65 .. 15 Memory Map Register Table ... 32 AD9269-40 .. 16 Memory Map Register Descriptions .. 34 AD9269-20 .. 17 Applications Information .. 36 Equivalent Circuits ... 18 Design Guidelines .. 36 Theory of Operation .. 19 Outline Dimensions ... 37 ADC Architecture .. 19 Ordering Guide .. 37 Analog Input Considerations .. 19 Voltage Reference ... 21
REVISION HISTORY 8/2016—Rev. 0 to Rev. A
Changes to Figure 3 ... 8 Updated Outline Dimensions ... 37
1/2010—Revision 0: Initial Version
Rev. A | Page 2 of 40 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9269-80 AD9269-65 AD9269-40 AD9269-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB (Pin 47) Bits [6:4]—Open Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 1—Open Bit 0—Disable SDIO Pull-Down QEC Control 0 (Register 0x110) Bits[7:6]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable QEC Control 1 (Register 0x111) Bits[7:3]—Open Bit 2—Force DC Bit 1—Force Phase Bit 0—Force Gain QEC Gain Bandwidth Control (Register 0x112) Bits[7:5]—Open Bits[4:0]—KEXP_GAIN QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bits[4:0]—KEXP_PHASE QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—KEXP_DC QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]—Initial Phase QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11B) Bits[13:0]—Initial DC I QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide
AD9269 Data Sheet TABLE OF CONTENTS
Features .. 1 Clock Input Considerations .. 22 Applications ... 1 Power Dissipation and Standby Mode .. 24 Functional Block Diagram .. 1 Digital Outputs ... 25 Product Highlights ... 1 Timing ... 25 Revision History ... 2 Built-In Self-Test (BIST) and Output Test .. 26 General Description ... 3 Built-In Self-Test (BIST) .. 26 Specifications ... 4 Output Test Modes ... 26 DC Specifications ... 4 Channel/Chip Synchronization .. 27 AC Specifications .. 6 DC and Quadrature Error Correction (QEC) .. 28 Digital Specifications ... 7 Serial Port Interface (SPI) .. 29 Switching Specifications .. 8 Configuration Using the SPI ... 29 Timing Specifications .. 9 Hardware Interface ... 29 Absolute Maximum Ratings .. 10 Configuration Without the SPI .. 30 Thermal Characteristics .. 10 SPI Accessible Features .. 30 ESD Caution .. 10 Memory Map .. 31 Pin Configuration and Function Descriptions ... 11 Reading the Memory Map Register Table ... 31 Typical Performance Characteristics ... 13 Open Locations .. 31 AD9269-80 .. 13 Default Values ... 31 AD9269-65 .. 15 Memory Map Register Table ... 32 AD9269-40 .. 16 Memory Map Register Descriptions .. 34 AD9269-20 .. 17 Applications Information .. 36 Equivalent Circuits ... 18 Design Guidelines .. 36 Theory of Operation .. 19 Outline Dimensions ... 37 ADC Architecture .. 19 Ordering Guide .. 37 Analog Input Considerations .. 19 Voltage Reference ... 21
REVISION HISTORY 8/2016—Rev. 0 to Rev. A
Changes to Figure 3 ... 8 Updated Outline Dimensions ... 37
1/2010—Revision 0: Initial Version
Rev. A | Page 2 of 40 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9269-80 AD9269-65 AD9269-40 AD9269-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB (Pin 47) Bits [6:4]—Open Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 1—Open Bit 0—Disable SDIO Pull-Down QEC Control 0 (Register 0x110) Bits[7:6]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable QEC Control 1 (Register 0x111) Bits[7:3]—Open Bit 2—Force DC Bit 1—Force Phase Bit 0—Force Gain QEC Gain Bandwidth Control (Register 0x112) Bits[7:5]—Open Bits[4:0]—KEXP_GAIN QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bits[4:0]—KEXP_PHASE QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—KEXP_DC QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]—Initial Phase QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11B) Bits[13:0]—Initial DC I QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide