Datasheet AD9261 (Analog Devices) - 7

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AD9261 SWITCHING SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted.
Table 5. Parameter1 T emp Min Typ Max Unit
CLOCK INPUT (USING CLOCK MULTIPLIER) Conversion Rate Full 30 160 MSPS CLK± Period Full 6.25 33 ns CLK± Duty Cycle Full 40 50 60 % CLOCK INPUT (DIRECT CLOCKING) Conversion Rate Full 608 640 672 MSPS CLK± Period Full 1.49 1.5625 1.64 ns CLK± Duty Cycle Full 40 50 60 % DATA OUTPUT PARAMETERS Output Data Rate Full 20 168 MSPS DCO to Data Skew (tSKEW)2 Full 3 ns Sample Latency Full 960 Cycles WAKE-UP TIME3 Full Power Down Power Full 3 μs Standby Power Full 9 μs Sleep Power Full 15 μs OUT-OF-RANGE RECOVERY TIME Full 960 Cycles SERIAL PORT INTERFACE4 SCLK Period Full 40 ns SCLK Pulse Width High Time (tSHIGH) Full 16 ns SCLK Pulse Width Low Time (tSLOW) Full 16 ns SDIO to SCLK Setup Time (tSDS) Full 5 ns SDIO to SCLK Hold Time (tSDH) Full 2 ns CSB to SCLK Setup Time (tSS) Full 5 ns CSB to SCLK Hold Time (tSH) Full 2 ns 1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data skew is measured from DCO 50% transition to data (D0 to D15) 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 μF capacitor on VREF and CFILT. 4 See Figure 50 and the Serial Port Interface (SPI) section.
Timing Diagram DCO tSKEW
2 -00 3
D0 TO D15
80 07 Figure 2. Timing Diagram Rev. 0 | Page 6 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide