Datasheet AD9266 (Analog Devices) - 5

AD9266 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.
Table 1. AD9266-20/AD9266-40 AD9266-65 AD9266-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full +0.05 ±0.30 +0.05 ±0.30 +0.05 ±0.30 % FSR Gain Error1 Full −2.5/−2.0 −1.0 +1.0 % FSR Differential Nonlinearity Full −0.9/+1.2 −0.9/+1.7 −0.9/+1.7 LSB (DNL)2 25°C −0.5/+0.6 −0.5/+1.0 −0.6/+1.1 LSB Integral Nonlinearity Full ±5.5 ±6.5 ±6.2 LSB (INL)2 25°C ±1.8 ±2.4 ±3.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.983 0.995 1.007 0.983 0.995 1.007 0.983 0.995 1.007 V Load Regulation Error Full 2 2 2 mV at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V 25°C 2.8 2.8 2.8 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6.5 6.5 6.5 pF Input Common-Mode Full 0.9 0.9 0.9 V Voltage Input Common-Mode Full 0.5 1.3 0.5 1.3 0.5 1.3 V Range REFERENCE INPUT Full 7.5 7.5 7.5 kΩ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current IAVDD2 Full 31.4/40.7 33.2/42.5 54.5 57.6 62.5 65.7 mA IDRVDD2 (1.8 V) Full 1.7/3.3 5.2 6.3 mA IDRVDD2 (3.3 V) Full 3.0/5.9 9.3 11.6 mA POWER CONSUMPTION DC Input Full 57/73 98 113 mW Sine Wave Input2 Full 60/79 63/82 107 113 124 130 mW (DRVDD = 1.8 V) Sine Wave Input2 Full 66/93 129 151 mW (DRVDD = 3.3 V) Standby Power4 Full 40 44 44 mW Power-Down Power Full 0.5 0.5 0.5 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between the differential inputs. 4 Standby power is measured with a dc input and the CLK active. Rev. B | Page 4 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AD9266-65 AD9266-40 AD9266-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE