Datasheet AD9644 (Analog Devices)

14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter (ADC) Data Sheet AD9644 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND JESD204A coded serial digital outputs SNR = 73.7 dBFS at 70 MHz and 80 MSPS AD9644 SNR = 71.7 dBFS at 70 MHz and 155 MSPS DOUT+A VIN+A 14 IT DOUT–A SFDR = 92 dBc at 70 MHz and 80 MSPS PIPELINE R AND VIN–A 14-BIT ADC E S DSYNC+A /10-B SFDR = 92 dBc at 70 MHz and 155 MSPS T IZL VCMA DSYNC–A BI IA IVER Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS R R E D DOUT+B L 1.8 V supply operation , S VIN+B 14 M PIPELINE 204A 8- DOUT–B D NG C Integer 1-to-8 input clock divider 14-BIT ADC S VIN–B DI DSYNC+B JE IF sampling frequencies to 250 MHz VCMB CO DSYNC–B −148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS REFERENCE −150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS PLL Programmable internal ADC voltage reference Flexible analog input range: 1.4 V p-p to 2.1 V p-p PDWN SERIAL PORT 1 TO 8 (SPI) CLOCK ADC clock duty cycle stabilizer DIVIDER Serial port control
1
User-configurable, built-in self-test (BIST) capability
-00 80
SCLK SDIO CSB CLK+ CLK– SYNC
91 0
Energy-saving power-down modes
Figure 1. 48-Lead 7 mm × 7 mm LFCSP
APPLICATIONS Communications PRODUCT HIGHLIGHTS Diversity radio systems
1. An on-chip PLL allows users to provide a single ADC
Multimode digital receivers (3G and 4G)
sampling clock; the PLL multiplies the ADC sampling
GSM, EDGE, W-CDMA, LTE,
clock to produce the corresponding JESD204A data rate
CDMA2000, WiMAX, TD-SCDMA
clock.
I/Q demodulation systems
2. The configurable JESD204A output block supports up to
Smart antenna systems
1.6 Gbps per channel data rate when using a dedicated
General-purpose software radios
data link per ADC or 3.2 Gbps data rate when using a
Broadband data applications
single shared data link for both ADCs.
Ultrasound equipment
3. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. 4. Operation from a single 1.8 V power supply. 5. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.
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Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Channel/Chip Synchronization Power Dissipation and Standby Mode Digital Outputs JESD204A Transmit Top Level Description Initial Frame Synchronization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable JESD204A Quick Configure (Register 0x5E) Bits[7:3]—Reserved Bits[2:0]—Register Quick Configuration JESD204A Lane Assignment (Register 0x5F) Bits[7:4]—Reserved Bits[3:0]—JESD204A Serial Lane Control JESD204A Link Control Register 1 (Register 0x60) Bit 7—Reserved Bit 6—Serial Tail Bit Enable Bit 5—Serial Test Sample Enable Bit 4—Serial Lane Synchronization Enable Bits[3:2]—Serial Lane Alignment Sequence Mode Bit 1—Frame Alignment Character Insertion Disable Bit 0—Serial Transmit Link Powered Down JESD204A Link Control Register 2 (Register 0x61) Bits[7:6]—Local DSYNC Mode Bit 5—DSYNC Pin Input Inverted Bit 4—CMOS DSYNC Input Bit 3—Open Bit 2—Bypass 8b/10b Encoding Bit 1—Invert Transmit Bits Bit 0—Mirror Serial Output Bits JESD204A Link Control Register 3 (Register 0x62) Bit 7—Disable CHKSUM Bit 6—Open Bits[5:4]—Link Test Generation Input Selection Bit 3—Open Bits[2:0]—Link Test Generation Mode JESD204A Link Control Register 4 (Register 0x63) Bits[7:0]—Initial Lane Alignment Sequence Repeat Count JESD204A Device Identification Number (DID) (Register 0x64) Bits[7:0]—Serial Device Identification (DID) Number JESD204A Bank Identification Number (BID) (Register 0x65) Bits[7:4]—Open Bits[3:0]—Serial Bank Identification (DID) Number JESD204A Lane Identification Number (LID) for Lane 0 (Register 0x66) Bits[7:5]—Open Bits[4:0]—Serial Lane Identification (LID) Number for Lane 0. JESD204A Lane Identification Number (LID) for Lane 1 (Register 0x67) Bits[7:5]—Open Bits[4:0]—Serial Lane Identification (LID) Number for Lane 1. JESD204A Scrambler (SCR) and Lane Configuration Registers (Register 0x6E) Bit 7—Enable Serial Scrambler Mode Bits[6:1]—Open Bit[0]—Serial Lane Control. JESD204A Number of Octets Per Frame (F) (Register 0x6F—Read Only) Bits[7:0]—Number of Octets per Frame (F) JESD204A Number of Frames Per Multiframe (Register 0x70) Bits[7:5]—Reserved Bits[4:0]—Number of Frames per Multiframe (K). JESD204A Number of Converters Per Link (M) (Register 0x71) Bits[7:1]—Reserved Bit 0—Number of Converters per Link per Device (M). JESD204A ADC Resolution (N) and Control Bits Per Sample (CS) (Register 0x72) Bits[7:6]—Number of Control Bits per Sample (CS) Bit 5—Open Bits[4:0]—Converter Resolution (N) JESD204A Total Bits Per Sample (N’) (Register 0x73) Bits[7:5]—Open Bits[4:0]—Total Number of Bits per Sample (N’) JESD204A Samples Per Converter (S) Frame Cycle (Register 0x74) Bits[7:5]—Open Bits[4:0]—Samples per Converter Frame Cycle (S) JESD204A HD and CF Configuration (Register 0x75) Bit 7—Enable High Density Format (Read Only) Bits[6:5]—Reserved Bits[4:0]—Number of Control Words per Frame Clock Cycle per Link (CF) JESD204A Serial Reserved Field 1 (Register 0x76) Bits[7:0]—Serial Reserved Field 1 (RES1) JESD204A Serial Reserved Field 2 (Register 0x77) Bits[7:0]—Serial Reserved Field 2 (RES2) JESD204A Serial Checksum Value for Lane 0 (Register 0x78) Bits[7:0]—Serial Checksum Value for Lane 0 JESD204A Serial Checksum Value for Lane 1 (Register 0x79) Bits[7:0]—Serial Checksum Value for Lane 1 Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCMA and VCMB SPI Port Outline Dimensions Ordering Guide