Datasheet AD7298-1 (Analog Devices) - 8

HerstellerAnalog Devices
Beschreibung8-Channel, 1 MSPS, 10-Bit SAR ADC
Seiten / Seite25 / 8 — AD7298-1. PIN CONFIGURATION AND FUNCTION DESCRIPTION. N0I. DRI. 15 SCLK. …
RevisionA
Dateiformat / GrößePDF / 776 Kb
DokumentenspracheEnglisch

AD7298-1. PIN CONFIGURATION AND FUNCTION DESCRIPTION. N0I. DRI. 15 SCLK. IN3. DOUT. IN4. 13 DIN. IN5. TOP VIEW. (Not to Scale). 12 NC. IN6. 11 CS

AD7298-1 PIN CONFIGURATION AND FUNCTION DESCRIPTION N0I DRI 15 SCLK IN3 DOUT IN4 13 DIN IN5 TOP VIEW (Not to Scale) 12 NC IN6 11 CS

Modelllinie für dieses Datenblatt

Textversion des Dokuments

AD7298-1 PIN CONFIGURATION AND FUNCTION DESCRIPTION T E RS V N2 N1 I I N0I D/ DRI V V V P V 20 19 18 17 16 V 1 15 SCLK IN3 14 V 2 DOUT IN4 AD7298-1 V 3 13 DIN IN5 TOP VIEW (Not to Scale) V 4 12 NC IN6 V 5 11 CS IN7 6 7 8 9 10 F DD RE ND ND1 CAP V V G G D NOTES 1. NC = NO CONNECT. 2. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE SHOULD BE SOLDERED
003
TO PCB GROUND FOR PROPER FUNCTIONALITY AND HEAT DISSIPATION.
09321- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 to 5, V , V Analog Inputs. The AD7298-1 has eight single-ended analog inputs that are multiplexed into the on-chip track- IN3 IN4 18 to 20 V , V , and-hold. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should be IN5 IN6 V , V , IN7 IN0 connected to GND1 to avoid noise pickup. V , V IN1 IN2 6 GND1 Ground. Ground reference point for the internal reference circuitry on the AD7298-1. The external reference signals and all analog input signals should be referred to the GND1 voltage. The GND1 pin should be connected to the ground plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. The V pin should be decoupled to this ground pin via a 10 µF REF decoupling capacitor. 7 V Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin. REF Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best performance, it is recommended to use a 10 µF decoupling capacitor on this pin to GND1. The internal reference can be disabled and an external reference supplied to this pin, if required. The input voltage range for the external reference is 2.0 V to 2.5 V. 8 D Decoupling Capacitor Pins. Decoupling capacitors (1 µF recommended) are connected to this pin to decouple CAP the internal LDO. 9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7298-1. The GND pin should be connected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Both the D and V pins should be decoupled to this CAP DD GND pin. 10 V Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 µF and 100 nF decoupling capacitors. DD 11 CS Chip Select, Active Low Logic Input. This pin is edge triggered on the falling edge of this input, the track-and- hold goes into hold mode, and a conversion is initiated. This input also frames the serial data transfer. When CS is low, the output bus is enabled and the conversion result becomes available on the DOUT output. 12 NC No Connect. 13 D Data In, Logic Input. Data to be written to the AD7298-1 control register is provided on this input and is clocked IN into the register on the falling edge of SCLK. 14 DOUT Serial Data Output. The conversion result from the AD7298-1 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7298-1 consists of four address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data (MSB first). 15 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7298-1. Rev. A | Page 7 of 24 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Terminology Circuit Information Converter Operation Analog Input ADC Transfer Function VDRIVE The Internal or External Reference Control Register Modes of Operation Traditional Multichannel Mode of Operation Repeat Operation Power-Down Modes Normal Mode Partial Power-Down Mode Full Power-Down Mode Powering Up the AD7298-1 Reset Serial Interface Layout and Configuration Outline Dimensions Ordering Guide