Datasheet AD7298-1 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 8-Channel, 1 MSPS, 10-Bit SAR ADC |
| Seiten / Seite | 25 / 6 — AD7298-1. TIMING SPECIFICATIONS. Table 2. Parameter. Limit at T , T. … |
| Revision | A |
| Dateiformat / Größe | PDF / 776 Kb |
| Dokumentensprache | Englisch |
AD7298-1. TIMING SPECIFICATIONS. Table 2. Parameter. Limit at T , T. Unit. Test Conditions/Comments. MIN. MAX
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AD7298-1 TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V, VDRIVE = 1.65 V to 3.6 V, VREF = 2.5 V internal, TA = −40°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Parameter Limit at T , T Unit Test Conditions/Comments MIN MAX
t t + (16 × t ) µs max Conversion time CONVERT 2 SCLK 820 ns typ Each ADC channel V to V , f = 20 MHz IN0 IN7 SCLK f 1 50 kHz min Frequency of external serial clock SCLK 20 MHz max Frequency of external serial clock t 6 ns min Minimum quiet time required between the end of the serial read and the start of QUIET the next voltage conversion in repeat and nonrepeat mode. t 10 ns min 2 CS to SCLK setup time t 1 15 ns max Delay from 3 CS (falling edge) until DOUT three-state disabled t 1 Data access time after SCLK falling edge 4 35 ns max V = 1.65 V to 3 V DRIVE 28 ns max V = 3 V to 3.6 V DRIVE t 0.4 × t ns min SCLK low pulse width 5 SCLK t 0.4 × t ns min SCLK high pulse width 6 SCLK t 1 14 ns min SCLK to DOUT valid hold time 7 t 1 16/34 ns min/ns max SCLK falling edge to DOUT high impedance 8 t 5 ns min DIN setup time prior to SCLK falling edge 9 t 4 ns min DIN hold time after SCLK falling edge 10 t 1 30 ns max Delay from 11 CS rising edge to DOUT high impedance t 6 ms max Internal reference power-up time from full power-down POWER-UP 1 Measured with a load capacitance on DOUT of 15 pF. Rev. A | Page 5 of 24 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Terminology Circuit Information Converter Operation Analog Input ADC Transfer Function VDRIVE The Internal or External Reference Control Register Modes of Operation Traditional Multichannel Mode of Operation Repeat Operation Power-Down Modes Normal Mode Partial Power-Down Mode Full Power-Down Mode Powering Up the AD7298-1 Reset Serial Interface Layout and Configuration Outline Dimensions Ordering Guide
AD7298-1 TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V, VDRIVE = 1.65 V to 3.6 V, VREF = 2.5 V internal, TA = −40°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Parameter Limit at T , T Unit Test Conditions/Comments MIN MAX
t t + (16 × t ) µs max Conversion time CONVERT 2 SCLK 820 ns typ Each ADC channel V to V , f = 20 MHz IN0 IN7 SCLK f 1 50 kHz min Frequency of external serial clock SCLK 20 MHz max Frequency of external serial clock t 6 ns min Minimum quiet time required between the end of the serial read and the start of QUIET the next voltage conversion in repeat and nonrepeat mode. t 10 ns min 2 CS to SCLK setup time t 1 15 ns max Delay from 3 CS (falling edge) until DOUT three-state disabled t 1 Data access time after SCLK falling edge 4 35 ns max V = 1.65 V to 3 V DRIVE 28 ns max V = 3 V to 3.6 V DRIVE t 0.4 × t ns min SCLK low pulse width 5 SCLK t 0.4 × t ns min SCLK high pulse width 6 SCLK t 1 14 ns min SCLK to DOUT valid hold time 7 t 1 16/34 ns min/ns max SCLK falling edge to DOUT high impedance 8 t 5 ns min DIN setup time prior to SCLK falling edge 9 t 4 ns min DIN hold time after SCLK falling edge 10 t 1 30 ns max Delay from 11 CS rising edge to DOUT high impedance t 6 ms max Internal reference power-up time from full power-down POWER-UP 1 Measured with a load capacitance on DOUT of 15 pF. Rev. A | Page 5 of 24 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Terminology Circuit Information Converter Operation Analog Input ADC Transfer Function VDRIVE The Internal or External Reference Control Register Modes of Operation Traditional Multichannel Mode of Operation Repeat Operation Power-Down Modes Normal Mode Partial Power-Down Mode Full Power-Down Mode Powering Up the AD7298-1 Reset Serial Interface Layout and Configuration Outline Dimensions Ordering Guide