Datasheet AD9467 (Analog Devices) - 4
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter |
| Seiten / Seite | 34 / 4 — AD9467. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 2/13—Rev. C to … |
| Revision | D |
| Dateiformat / Größe | PDF / 1.0 Mb |
| Dokumentensprache | Englisch |
AD9467. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 2/13—Rev. C to Rev. D. 2/11—Rev. 0 to Rev. A. 9/11—Rev. B to Rev. C
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AD9467 Data Sheet TABLE OF CONTENTS
Features .. 1 Equivalent Circuits ... 11 Applications ... 1 Typical Performance Characteristics ... 12 General Description ... 1 Theory of Operation .. 19 Functional Block Diagram .. 1 Analog Input Considerations ... 19 Product Highlights ... 1 Clock Input Considerations .. 22 Revision History ... 2 Serial Port Interface (SPI) .. 26 Specifications ... 3 Hardware Interface ... 26 AC Specifications .. 4 Memory Map .. 28 Digital Specifications ... 6 Reading the Memory Map Table .. 28 Switching Specifications .. 7 Reserved Locations .. 28 Absolute Maximum Ratings .. 8 Default Values ... 28 Thermal Impedance ... 8 Logic Levels ... 28 ESD Caution .. 8 Outline Dimensions ... 32 Pin Configuration and Function Descriptions ... 9 Ordering Guide .. 32
REVISION HISTORY 2/13—Rev. C to Rev. D 2/11—Rev. 0 to Rev. A
Changes to Figure 1 .. 1 Changes to Features Section .. 1 Changes to Figure 2 .. 7 Added Figure 24 and Figure 25; Renumbered Sequential y ... 14 Changes to VIN+, VIN− Parameter Rating, Table 5 ... 8 Changes to Differential Configurations Section and Changes to Figure 51, Figure 52, and Figure 53 ... 20 Figure 54 .. 21 Changes to Figure 54 and Figure 56 ... 21 Added Figure 55 to Figure 57 ... 21 Changes to Digital Outputs and Timing Section ... 24 Changes to Figure 65 and Figure 66 .. 24 Deleted Addr. (Hex) 17 Row, Table 13 ... 29 Changes to Addr. (Hex) 15, Bits[2:0], Addr. (Hex) 10, Bits[7:0], Updated Outline Dimensions ... 32 and Addr. (Hex) 10, Default Notes Column ... 29 Changes to Ordering Guide .. 32 Changes to Addr. (Hex) 36, Default Value (Hex) Column and Addr. (Hex) 107, Default Value (Hex) Column ... 30
9/11—Rev. B to Rev. C
Changes to Figure 44 and Figure 45 ... 17
10/10—Revision 0: Initial Version 3/11—Rev. A to Rev. B
Change Parameter Name to Ful Power Bandwidth, Table 1 .. 3 Changes to Switching Specifications, Table 4 ... 7 Change to VIN+, VIN− Parameter, Table 5 .. 8 Deleted Figure 43 .. 17 Added New Figure 43... 17 Rev. D | Page 2 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations SFDR Optimization—Buffer Current Adjustment Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power Supplies Full-Scale and Reference Options Digital Outputs and Timing Overrange (OR) Output Pins SPI Pins: SCLK, SDIO, CSB Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide
AD9467 Data Sheet TABLE OF CONTENTS
Features .. 1 Equivalent Circuits ... 11 Applications ... 1 Typical Performance Characteristics ... 12 General Description ... 1 Theory of Operation .. 19 Functional Block Diagram .. 1 Analog Input Considerations ... 19 Product Highlights ... 1 Clock Input Considerations .. 22 Revision History ... 2 Serial Port Interface (SPI) .. 26 Specifications ... 3 Hardware Interface ... 26 AC Specifications .. 4 Memory Map .. 28 Digital Specifications ... 6 Reading the Memory Map Table .. 28 Switching Specifications .. 7 Reserved Locations .. 28 Absolute Maximum Ratings .. 8 Default Values ... 28 Thermal Impedance ... 8 Logic Levels ... 28 ESD Caution .. 8 Outline Dimensions ... 32 Pin Configuration and Function Descriptions ... 9 Ordering Guide .. 32
REVISION HISTORY 2/13—Rev. C to Rev. D 2/11—Rev. 0 to Rev. A
Changes to Figure 1 .. 1 Changes to Features Section .. 1 Changes to Figure 2 .. 7 Added Figure 24 and Figure 25; Renumbered Sequential y ... 14 Changes to VIN+, VIN− Parameter Rating, Table 5 ... 8 Changes to Differential Configurations Section and Changes to Figure 51, Figure 52, and Figure 53 ... 20 Figure 54 .. 21 Changes to Figure 54 and Figure 56 ... 21 Added Figure 55 to Figure 57 ... 21 Changes to Digital Outputs and Timing Section ... 24 Changes to Figure 65 and Figure 66 .. 24 Deleted Addr. (Hex) 17 Row, Table 13 ... 29 Changes to Addr. (Hex) 15, Bits[2:0], Addr. (Hex) 10, Bits[7:0], Updated Outline Dimensions ... 32 and Addr. (Hex) 10, Default Notes Column ... 29 Changes to Ordering Guide .. 32 Changes to Addr. (Hex) 36, Default Value (Hex) Column and Addr. (Hex) 107, Default Value (Hex) Column ... 30
9/11—Rev. B to Rev. C
Changes to Figure 44 and Figure 45 ... 17
10/10—Revision 0: Initial Version 3/11—Rev. A to Rev. B
Change Parameter Name to Ful Power Bandwidth, Table 1 .. 3 Changes to Switching Specifications, Table 4 ... 7 Change to VIN+, VIN− Parameter, Table 5 .. 8 Deleted Figure 43 .. 17 Added New Figure 43... 17 Rev. D | Page 2 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations SFDR Optimization—Buffer Current Adjustment Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power Supplies Full-Scale and Reference Options Digital Outputs and Timing Overrange (OR) Output Pins SPI Pins: SCLK, SDIO, CSB Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide