Datasheet HMCAD1511 (Analog Devices) - 9

HMCAD1511
v04.1015
HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter Start up initialization
As part of the HMCAD1511 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. Make sure that the supply voltages are properly settled before the start up initialization is being performed. reset can be done in one of two ways: 1. By applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. By using the serial interface to set the ‘rst’ bit high. Internal registers are reset to default values when this bit is set. the ‘rst’ bit is self-reset to zero. When using this method, do not apply any low-going pulse on the resetn pin. Power down cycling can be done in one of two ways: 1. By applying a high-going pulse (minimum 20 ns) on the PD pin (asynchronous). 2. By cycling the ‘pd’ bit in register 0Fhex to high (reg value ‘0200’hex) and then low (reg value ‘0000’hex).
Serial interface
0 the HMCAD1511 configuration registers can be accessed through a serial interface formed by the pins sDAtA (serial interface data), sCLK (serial interface clock) and Csn (chip select, active low). the fol owing occurs when Csn is set low: t • Serial data are shifted into the chip M s • At every rising edge of SCLK, the value present at SDATA is latched • SDATA is loaded into the register every 24th rising edge of SCLK s - Multiples of 24-bit words data can be loaded within a single active Csn pulse. If more than 24 bits are loaded into r sDAtA during one active Csn pulse, only the first 24 bits are kept. the excess bits are ignored. every 24-bit word is e divided into two parts: t • The first eight bits form the register address r e • The remaining 16 bits form the register data v Acceptable sCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly control ed. n o
timing diagram
Figure 4 shows the timing of the serial port interface. table 4 explains the timing variables used in figure 4. tchi tcs thi tck ts tch CSN t t lo h A / D C SCLK SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 3: serial Port Interface timing
table 4: Serial port interface timing definitions Parameter Description Minimum value Unit
t setup time between Csn and sCLK 8 ns cs t Hold time between Csn and sCLK 8 ns ch t sCLK high time 20 ns hi t sCLK low time 20 ns lo t sCLK period 50 ns ck t Data setup time 5 ns s t Data hold time 5 ns h Informatio For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, n furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Phone: 781-329-4700 • Order online at www.analog.com
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