Datasheet AD9484 (Analog Devices) - 7

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AD9484 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
Maximum Conversion Rate Full 500 MSPS Minimum Conversion Rate Full 50 MSPS CLK+ Pulse Width High (tCH)1 Full 0.9 11 ns CLK+ Pulse Width Low (tCL)1 Full 0.9 11 ns Output (LVDS—SDR)1 Data Propagation Delay (tPD) Full 0.85 ns Rise Time (tR) (20% to 80%) 25°C 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 ns DCO Propagation Delay (tCPD) Full 0.6 ns Data to DCO Skew (tSKEW) Full −0.07 +0.07 ns Latency Full 15 Clock cycles Aperture Time (tA) 25°C 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 fs rms 1 See Figure 2.
Timing Diagram N – 1 t N + 4 A N + 5 N N + 3 VIN+, VIN– N + 1 N + 2 tCH tCL 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD Dx+ N – 15 N – 14 N – 13 N – 12 N – 11
002
Dx–
615- 09 Figure 2. Timing Diagram Rev. A | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE