Datasheet AD9643 (Analog Devices) - 36

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AD9643 Data Sheet OUTLINE DIMENSIONS 9.10 0.30 9.00 SQ 0.60 MAX 0.25 8.90 0.60 0.18 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 6.35 8.75 SQ BSC PAD 6.20 SQ 8.65 6.05 0.50 33 0.40 16 32 17 0.30 0.25 MIN TOP VIEW BOTTOM VIEW 7.50 REF 12° MAX 0.80 MAX 1.00 0.65 TYP 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING FUNCTION DESCRIPTIONS 0.20 REF PLANE SECTION OF THIS DATA SHEET. C 2012- 12- COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-
Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option
AD9643BCPZ-170 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZ-210 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZ-250 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZRL7-170 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZRL7-210 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643BCPZRL7-250 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9643-170EBZ −40°C to +85°C Evaluation Board with AD9643-170 AD9643-210EBZ −40°C to +85°C Evaluation Board with AD9643-210 AD9643-250EBZ −40°C to +85°C Evaluation Board with AD9643-250 1 Z = RoHS Compliant Part.
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Rev. E | Page 36 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide