Datasheet AD9634 (Analog Devices) - 8

link to page 8
Data Sheet AD9634 SWITCHING SPECIFICATIONS Table 4. AD9634-170 AD9634-210 AD9634-250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS1 Input Clock Rate Full 625 625 625 MHz Conversion Rate2 DCS Enabled Full 40 170 40 210 40 250 MSPS DCS Disabled Full 10 170 10 210 10 250 MSPS CLK Period, Divide-by-1 Mode (tCLK) Full 5.8 4.8 4 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Full 0.8 0.8 0.8 ns Divide-by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS1 Data Propagation Delay (tPD) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns DCO Propagation Delay (tDCO) Full 4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns DCO to Data Skew (tSKEW) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Wake-Up Time (from Standby) Full 10 10 10 µs Wake-Up Time (from Power-Down) Full 100 100 100 µs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 See Figure 2. 2 Conversion rate is the clock rate after the divider.
Timing Diagram N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO– DCO+ tSKEW tPD D0±/D1± D0 D1 D0 D1 D0 D1 D0 D1 D0 EVEN/ODD (LSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 D10±/D11±
002
D10 D11 D10 D11 D10 D11 D10 D11 D10 (MSB) N – 10 N – 10 N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6
09996- Figure 2. Even/Odd LVDS Mode Data Output Timing Rev. B | Page 7 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE