Data SheetAD9642SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p ful -scale input range, DCS enabled, unless otherwise noted. Table 1.AD9642-170AD9642-210AD9642-250ParameterTemperatureMinTypMaxMinTypMaxMinTypMaxUnit RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±11 ±11 ±10 mV Gain Error Full +2/−11 +3.5/−8 +3/−7 %FSR Differential Nonlinearity (DNL) Full ±0.5 ±0.55 ±0.6 LSB 25°C ±0.3 ±0.3 ±0.32 LSB Integral Nonlinearity (INL)1 Full ±1.3 ±2.0 ±2.5 LSB 25°C ±0.6 ±0.75 ±1.0 LSB TEMPERATURE DRIFT Offset Error Full ±7 ±7 ±7 ppm/°C Gain Error Full ±52 ±105 ±75 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.83 0.85 0.85 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 2.5 pF Input Resistance3 Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current I 1 AVDD Full 123 136 129 139 136 146 mA I 1 DRVDD Full 50 64 56 67 64 69 mA POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Full 311 360 333 371 360 387 mW Standby Power4 Full 50 50 50 mW Power-Down Power Full 5 5 5 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND). Rev. B | Page 3 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE