Datasheet AD9633 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | Quad, 12-Bit, 80/105/125 MSPS Serial LVDS 1.8 V A/D Converter |
| Seiten / Seite | 42 / 3 — AD9633. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 10/15—Rev. A to … |
| Revision | C |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
AD9633. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 10/15—Rev. A to Rev. B. 9/14—Rev. 0 to Rev. A
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AD9633 Data Sheet TABLE OF CONTENTS
Features .. 1 Clock Input Considerations .. 24 Applications ... 1 Power Dissipation and Power-Down Mode ... 26 General Description ... 1 Digital Outputs and Timing ... 27 Functional Block Diagram .. 1 Output Test Modes ... 30 Product Highlights ... 1 Serial Port Interface (SPI) .. 31 Revision History ... 2 Configuration Using the SPI ... 31 Specifications ... 3 Hardware Interface ... 32 DC Specifications ... 3 Configuration Without the SPI .. 32 AC Specifications .. 4 SPI Accessible Features .. 32 Digital Specifications ... 5 Memory Map .. 33 Switching Specifications .. 6 Reading the Memory Map Register Table ... 33 Timing Specifications .. 7 Memory Map Register Table ... 34 Absolute Maximum Ratings .. 11 Memory Map Register Descriptions .. 37 Thermal Resistance .. 11 Applications Information .. 39 ESD Caution .. 11 Design Guidelines .. 39 Pin Configuration and Function Descriptions ... 12 Power and Ground Recommendations ... 39 Typical Performance Characteristics ... 14 Clock Stability Considerations ... 39 AD9633-80 .. 14 Exposed Pad Thermal Heat Slug Recommendations .. 39 AD9633-105 .. 16 VCM ... 39 AD9633-125 .. 18 Reference Decoupling .. 39 Equivalent Circuits ... 21 SPI Port .. 39 Theory of Operation .. 22 Crosstalk Performance .. 40 Analog Input Considerations .. 22 Outline Dimensions ... 41 Voltage Reference ... 23 Ordering Guide .. 41
REVISION HISTORY 10/15—Rev. A to Rev. B
Changes to Pin 9 to Pin 14 and Pin 23 to Pin 28 Descriptions .. 12 Added Note 4, Table 4 .. 6 Changes to Figure 47 and Figure 48 .. 21 Changes to Digital Outputs and Timing Section ... 28 Changes to Clock Input Options Section .. 24 Changes to Clock Stability Considerations Section ... 39 Changes to Jitter Considerations Section .. 26 Changes to Digital Outputs and Timing Section ... 27
9/14—Rev. 0 to Rev. A
Changes to Table 12 ... 29 Changes to Table 2 .. 4 Changes to Channel-Specific Registers Section ... 33 Added Propagation Delay Parameters of 1.5 ns (min) Changes to Output Phase (Register 0x16) Section .. 37 and 3.1 ns (max); Table 4 ... 6 Changes to Resolution/Sample Rate Override (Register 0x100) Changed tSSYNC from 0.24 ns Typ to 1.2 ns Min and Changed Section .. 38 tHSYNC from 0.40 ns Typ to −0.2 ns Min; Table 5 and Changes to Added Clock Stability Considerations Section... 39 Figure 2 .. 7 Updated Outline Dimensions ... 41 Changes to Figure 3 and Figure 4 ... 8 Changes to Figure 5 .. 9
10/11—Revision 0: Initial Version
Rev. B | Page 2 of 41 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9633-80 AD9633-105 AD9633-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide
AD9633 Data Sheet TABLE OF CONTENTS
Features .. 1 Clock Input Considerations .. 24 Applications ... 1 Power Dissipation and Power-Down Mode ... 26 General Description ... 1 Digital Outputs and Timing ... 27 Functional Block Diagram .. 1 Output Test Modes ... 30 Product Highlights ... 1 Serial Port Interface (SPI) .. 31 Revision History ... 2 Configuration Using the SPI ... 31 Specifications ... 3 Hardware Interface ... 32 DC Specifications ... 3 Configuration Without the SPI .. 32 AC Specifications .. 4 SPI Accessible Features .. 32 Digital Specifications ... 5 Memory Map .. 33 Switching Specifications .. 6 Reading the Memory Map Register Table ... 33 Timing Specifications .. 7 Memory Map Register Table ... 34 Absolute Maximum Ratings .. 11 Memory Map Register Descriptions .. 37 Thermal Resistance .. 11 Applications Information .. 39 ESD Caution .. 11 Design Guidelines .. 39 Pin Configuration and Function Descriptions ... 12 Power and Ground Recommendations ... 39 Typical Performance Characteristics ... 14 Clock Stability Considerations ... 39 AD9633-80 .. 14 Exposed Pad Thermal Heat Slug Recommendations .. 39 AD9633-105 .. 16 VCM ... 39 AD9633-125 .. 18 Reference Decoupling .. 39 Equivalent Circuits ... 21 SPI Port .. 39 Theory of Operation .. 22 Crosstalk Performance .. 40 Analog Input Considerations .. 22 Outline Dimensions ... 41 Voltage Reference ... 23 Ordering Guide .. 41
REVISION HISTORY 10/15—Rev. A to Rev. B
Changes to Pin 9 to Pin 14 and Pin 23 to Pin 28 Descriptions .. 12 Added Note 4, Table 4 .. 6 Changes to Figure 47 and Figure 48 .. 21 Changes to Digital Outputs and Timing Section ... 28 Changes to Clock Input Options Section .. 24 Changes to Clock Stability Considerations Section ... 39 Changes to Jitter Considerations Section .. 26 Changes to Digital Outputs and Timing Section ... 27
9/14—Rev. 0 to Rev. A
Changes to Table 12 ... 29 Changes to Table 2 .. 4 Changes to Channel-Specific Registers Section ... 33 Added Propagation Delay Parameters of 1.5 ns (min) Changes to Output Phase (Register 0x16) Section .. 37 and 3.1 ns (max); Table 4 ... 6 Changes to Resolution/Sample Rate Override (Register 0x100) Changed tSSYNC from 0.24 ns Typ to 1.2 ns Min and Changed Section .. 38 tHSYNC from 0.40 ns Typ to −0.2 ns Min; Table 5 and Changes to Added Clock Stability Considerations Section... 39 Figure 2 .. 7 Updated Outline Dimensions ... 41 Changes to Figure 3 and Figure 4 ... 8 Changes to Figure 5 .. 9
10/11—Revision 0: Initial Version
Rev. B | Page 2 of 41 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9633-80 AD9633-105 AD9633-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide