Datasheet AD9637 (Analog Devices)

Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter Data Sheet AD9637 FEATURES FUNCTIONAL BLOCK DIAGRAM Low power: 60 mW per channel at 80 MSPS with scalable AVDD PDWN DRVDD power options AD9637 12 D+ A VIN+ A SNR = 71.5 dBFS (to Nyquist) ADC SERIAL D– A VIN– A LVDS SFDR = 92 dBc (to Nyquist) 12 D+ B DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) VIN+ B ADC SERIAL D– B VIN– B LVDS Serial LVDS (ANSI-644, default) 12 Low power, reduced signal option (similar to IEEE 1596.3) D+ C VIN+ C ADC SERIAL D– C VIN– C LVDS Data and frame clock outputs 650 MHz full power analog bandwidth 12 D+ D VIN+ D ADC SERIAL D– D 2 V p-p differential input voltage range VIN– D LVDS 1.8 V supply operation 12 D+ E VIN+ E ADC SERIAL D– E Serial port control VIN– E LVDS Full chip and individual channel power-down modes 12 D+ F VIN+ F SERIAL Flexible bit orientation ADC D– F VIN– F LVDS Built-in and custom digital test pattern generation 12 D+ G Programmable clock and data alignment VIN+ G ADC SERIAL D– G VIN– G LVDS Programmable output resolution 12 D+ H Standby mode VIN+ H ADC SERIAL D– H VIN– H LVDS APPLICATIONS VREF Medical imaging and nondestructive ultrasound SENSE FCO+ 1.0V DATA FCO– Portable ultrasound and digital beam-forming systems VCM REF SERIAL PORT RATE DCO+ SELECT INTERFACE MULTIPLIER Quadrature radio receivers DCO– SYNC Diversity radio receivers
01
RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK–
-0
Optical networking
215
DFS DTP
10
Test equipment
Figure 1.
GENERAL DESCRIPTION
The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital clock and data alignment and programmable digital test pattern converter (ADC) with an on-chip sample-and-hold circuit generation. The available digital test patterns include built-in designed for low cost, low power, small size, and ease of use. deterministic and pseudorandom patterns, along with custom user- The product operates at a conversion rate of up to 80 MSPS and defined test patterns entered via the serial port interface (SPI). is optimized for outstanding dynamic performance and low The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is power in applications where a small package size is critical. specified over the industrial temperature range of −40°C to +85°C. The ADC requires a single 1.8 V power supply and LVPECL-/ This product is protected by a U.S. patent. CMOS-/LVDS-compatible sample rate clock for full performance
PRODUCT HIGHLIGHTS
operation. No external reference or driver components are 1. Small Footprint. Eight ADCs are contained in a small, required for many applications. space-saving package. The ADC automatically multiplies the sample rate clock for the 2. Low Power of 60 mW/Channel at 80 MSPS with Scalable appropriate LVDS serial data rate. A data clock output (DCO) for Power Options. capturing data on the output and a frame clock output (FCO) for 3. Ease of Use. A data clock output (DCO) is provided that signaling a new output byte are provided. Individual channel operates at frequencies of up to 480 MHz and supports power-down is supported and typically consumes less than 2 mW double data rate (DDR) operation. when all channels are disabled. 4. User Flexibility. The SPI control offers a wide range of The ADC contains several features designed to maximize flexible features to meet specific system requirements. flexibility and minimize system cost, such as programmable 5. Pin Compatible with the AD9257 (14-Bit Octal ADC).
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide