Datasheet AD9635 (Analog Devices)

Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9635 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V supply operation AVDD AGND DRVDD Low power: 115 mW per channel at 125 MSPS with scalable AD9635 D0A+ power options 12 D0A– SNR = 71 dBFS (to Nyquist) VINA+ 12-BIT PIPELINE D1A+ ADC SFDR = 93 dBc at 70 MHz VINA– D1A– 12 DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical) RS D0B+ VCM E R AND DDR V Serial LVDS (ANSI-644, default) and low power, reduced E D0B– 12 IZ DRI D1B+ range option (similar to IEEE 1596.3) VINB+ 12-BIT PIPELINE AL ADC RI DS D1B– V 650 MHz full power analog bandwidth VINB– E L 12 DCO+ , S 2 V p-p input voltage range L L DCO– P Serial port control REFERENCE FCO+ Full chip and individual channel power-down modes FCO– Flexible bit orientation Built-in and custom digital test pattern generation SERIAL PORT 1 TO 8 INTERFACE CLOCK DIVIDER Clock divider Programmable output clock and data alignment
001
Programmable output resolution SCLK/ SDIO/ CSB CLK+ CLK– DFS PDWN
10577-
Standby mode
Figure 1.
APPLICATIONS
The ADC automatically multiplies the sample rate clock for the
Communications
appropriate LVDS serial data rate. A data clock output (DCO) for
Diversity radio systems
capturing data on the output and a frame clock output (FCO) for
Multimode digital receivers
signaling a new output byte are provided. Individual channel
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
power-down is supported; the AD9635 typical y consumes less
I/Q demodulation systems
than 2 mW in the full power-down state. The ADC provides
Smart antenna systems
several features designed to maximize flexibility and minimize
Broadband data applications
system cost, such as programmable output clock and data align-
Battery-powered instruments
ment and digital test pattern generation. The available digital
Handheld scope meters
test patterns include built-in deterministic and pseudorandom
Portable medical imaging and ultrasound
patterns, along with custom user-defined test patterns entered via
Radar/LIDAR
the serial port interface (SPI).
GENERAL DESCRIPTION
The AD9635 is available in a RoHS-compliant, 32-lead LFCSP. The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to- It is specified over the industrial temperature range of −40°C digital converter (ADC) with an on-chip sample-and-hold circuit to +85°C. designed for low cost, low power, small size, and ease of use.
PRODUCT HIGHLIGHTS
The product operates at a conversion rate of up to 125 MSPS 1. Small Footprint. Two ADCs are contained in a smal , space- and is optimized for outstanding dynamic performance and low saving package. power in applications where a small package size is critical. 2. Low Power. The AD9635 uses 115 mW/channel at 125 MSPS The ADC requires a single 1.8 V power supply and LVPECL-/ with scalable power options. CMOS-/LVDS-compatible sample rate clock for ful performance 3. Pin Compatibility with the AD9645, a 14-Bit Dual ADC. operation. No external reference or driver components are 4. Ease of Use. A data clock output (DCO) operates at required for many applications. frequencies of up to 500 MHz and supports double data rate (DDR) operation. 5. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE