Datasheet AD9250 (Analog Devices)

14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9250 FEATURES FUNCTIONAL BLOCK DIAGRAM JESD204B Subclass 0 or Subclass 1 coded serial digital outputs AVDD DRVDD DVDD AGND DGND DRGND Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and AD9250 250 MSPS VIN+A Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz PIPELINE JESD204B SERDOUT0± 14-BIT ADC INTERFACE VIN–A AIN and 250 MSPS CML, TX OUTPUTS VCM HIGH Total power consumption: 711 mW at 250 MSPS SPEED SERIALIZERS SERDOUT1± VIN+B PIPELINE 1.8 V supply voltages 14-BIT ADC VIN–B Integer 1-to-8 input clock divider CMOS Sample rates of up to 250 MSPS CONTROL DIGITAL REGISTERS INPUT PDWN IF sampling frequencies of up to 400 MHz SYSREF± Internal analog-to-digital converter (ADC) voltage reference SYNCINB± CLOCK GENERATION CMOS CLK± FAST FDA Flexible analog input range DIGITAL DETECT RFCLK OUTPUT FDB CMOS DIGITAL 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) INPUT/OUTPUT ADC clock duty cycle stabilizer (DCS)
001
95 dB channel isolation/crosstalk RST SDIO SCLK CS
10559-
Serial port control
Figure 1.
Energy saving power-down modes PRODUCT HIGHLIGHTS APPLICATIONS
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
Diversity radio systems
2. The configurable JESD204B output block supports up to
Multimode digital receivers (3G)
5 Gbps per lane.
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
3. An on-chip, phase-locked loop (PLL) al ows users to provide
DOCSIS 3.0 CMTS upstream receive paths
a single ADC sampling clock; the PLL multiplies the ADC
HFC digital reverse path receivers
sampling clock to produce the corresponding JESD204B
I/Q demodulation systems
data rate clock.
Smart antenna systems
4. Support for an optional RF clock input to ease system board
Electronic test and measurement equipment
design.
Radar receivers
5. Proprietary differential input maintains excel ent SNR
COMSEC radio architectures
performance for input frequencies of up to 400 MHz.
IED detection/jamming systems
6. Operation from a single 1.8 V power supply.
General-purpose software radios
7. Standard serial port interface (SPI) that supports various
Broadband data applications
product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration. This product may be protected by one or more U.S. or international patents.
Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide