Datasheet AD9249 (Analog Devices) - 10

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Data Sheet AD9249 TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS See Figure 50 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB1/CSB2 and SCLK 2 ns min tH Hold time between CSB1/CSB2 and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output 10 ns min relative to the SCLK falling edge (not shown in Figure 50) tDIS_SDIO Time required for the SDIO pin to switch from an output to an input 10 ns min relative to the SCLK rising edge (not shown in Figure 50)
SYNC Timing Diagram CLK+ t t SSYNC HSYNC
004
SYNC
1536- 1 Figure 5. SYNC Input Timing Requirements Rev. 0 | Page 9 of 36 Document Outline Features Applications General Description Simplified Functional Block Diagram Product Highlights Revision History Functional Block Diagram Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Timing Specifications SYNC Timing Diagram Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel Specific Registers Memory Map Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—FCO±x, DCO±x Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Board Layout Considerations Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock Clock Stability Considerations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide