Datasheet AD9249 (Analog Devices) - 8

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Data Sheet AD9249 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4. Parameter1, 2 Symbol Temp Min Typ Max Unit
CLOCK3 Input Clock Rate Full 10 520 MHz Conversion Rate Full 10 65 MSPS Clock Pulse Width High tEH Full 7.69 ns Clock Pulse Width Low tEL Full 7.69 ns OUTPUT PARAMETERS3 Propagation Delay tPD Full 1.5 2.3 3.1 ns Rise Time (20% to 80%) tR Full 300 ps Fall Time (20% to 80%) tF Full 300 ps FCO±1, FCO±2 Propagation Delay tFCO Full 1.5 2.3 3.1 ns DCO±1, DCO±2 Propagation Delay4 tCPD Full tFCO + (tSAMPLE/28) ns DCO±1, DCO±2 to Data Delay4 tDATA Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO±1, DCO±2 to FCO±1, FCO±2 Delay4 tFRAME Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data to Data Skew tDATA-MAX − tDATA-MIN Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 35 μs Wake-Up Time (Power-Down)5 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay tA 25°C 1 ns Aperture Uncertainty (Jitter) tJ 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Adjustable using the SPI. 4 tSAMPLE/28 is based on the number of bits, divided by 2, because the delays are based on half duty cycles. tSAMPLE = 1/fSAMPLE. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. 0 | Page 7 of 36 Document Outline Features Applications General Description Simplified Functional Block Diagram Product Highlights Revision History Functional Block Diagram Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Timing Specifications SYNC Timing Diagram Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel Specific Registers Memory Map Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—FCO±x, DCO±x Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Board Layout Considerations Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock Clock Stability Considerations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide