Datasheet AD9249 (Analog Devices)

16 Channel, 14-Bit, 65 MSPS, Serial LVDS, 1.8 V ADC Data Sheet AD9249 FEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM Low power AVDD PDWN DRVDD 16 ADC channels integrated into 1 package AD9249 D+A1 VIN+A1 14 SERIAL 58 mW per channel at 65 MSPS with scalable power options ADC D–A1 VIN–A1 LVDS 35 mW per channel at 20 MSPS D+A2 VIN+A2 14 SERIAL ADC D–A2 VIN–A2 LVDS SNR: 75 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist) DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical) Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB D+H1 VIN+H1 14 SERIAL ADC D–H1 typical VIN–H1 LVDS D+H2 VIN+H2 14 Serial LVDS (ANSI-644, default) SERIAL ADC D–H2 VIN–H2 LVDS Low power, reduced signal option (similar to IEEE 1596.3) VREF Data and frame clock outputs SENSE FCO+1, FCO+2 1.0V 650 MHz full power analog bandwidth DATA FCO–1, FCO–2 VCM1, VCM2 REF RATE SERIAL PORT SELECT MULTIPLIER DCO+1, DCO+2 2 V p-p input voltage range INTERFACE DCO–1, DCO–2 SYNC 1.8 V supply operation
200
RBIAS1, GND CSB1, SDIO/ SCLK/ CLK+ CLK– Serial port control RBIAS2 CSB2 DFS DTP
11536-
Flexible bit orientation
Figure 1.
Built in and custom digital test pattern generation Programmable clock and data alignment Power-down and standby modes APPLICATIONS Medical imaging
The ADC contains several features designed to maximize
Communications receivers
flexibility and minimize system cost, such as programmable
Multichannel data acquisition
clock and data alignment and programmable digital test pattern
GENERAL DESCRIPTION
generation. The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital The available digital test patterns include built-in deterministic converter (ADC) with an on-chip sample-and-hold circuit that and pseudorandom patterns, along with custom user-defined test is designed for low cost, low power, small size, and ease of use. patterns entered via the serial port interface (SPI). The device operates at a conversion rate of up to 65 MSPS and The AD9249 is available in an RoHS-compliant, 144-bal CSP- is optimized for outstanding dynamic performance and low power BGA. It is specified over the industrial temperature range of −40°C in applications where a small package size is critical. to +85°C. This product is protected by a U.S. patent. The ADC requires a single 1.8 V power supply and an LVPECL-/
PRODUCT HIGHLIGHTS
CMOS-/LVDS-compatible sample rate clock for full performance 1. Small Footprint. Sixteen ADCs are contained in a small, operation. No external reference or driver components are 10 mm × 10 mm package. required for many applications. 2. Low Power. 35 mW/channel at 20 MSPS with scalable power The AD9249 automatical y multiplies the sample rate clock for the options. appropriate LVDS serial data rate. Data clock outputs (DCO±1, 3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate DCO±2) for capturing data on the output and frame clock outputs at frequencies of up to 455 MHz and support double data (FCO±1, FCO±2) for signaling a new output byte are provided. rate (DDR) operation. Individual channel power-down is supported, and the device 4. User Flexibility. SPI control offers a wide range of flexible typically consumes less than 2 mW when all channels are disabled. features to meet specific system requirements.
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Document Outline Features Applications General Description Simplified Functional Block Diagram Product Highlights Revision History Functional Block Diagram Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Timing Specifications SYNC Timing Diagram Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel Specific Registers Memory Map Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—FCO±x, DCO±x Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Board Layout Considerations Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock Clock Stability Considerations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide