Datasheet AD9681 (Analog Devices) - 9

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AD9681 Data Sheet TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 1.2 ns min tHSYNC SYNC to rising edge of CLK+ hold time −0.2 ns min SPI TIMING REQUIREMENTS See Figure 53 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB1/CSB2 and SCLK 2 ns min tH Hold time between CSB1/CSB2 and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the 10 ns min SCLK falling edge (not shown in Figure 53) tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the 10 ns min SCLK rising edge (not shown in Figure 53)
Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 21 for SPI register setting of output modes.
N – 1 VIN±x1, VIN±x2 N t N + 1 A t t CLK– EH EL CLK+ t DCO–1, DCO–2 CPD DDR DCO+1, DCO+2 DCO–1, DCO–2 SDR DCO+1, DCO+2 tFCO tFRAME FCO–1, FCO–2 FCO+1, FCO+2 tPD t D0–A1 DATA BITWISE D12 D10 D08 D06 D04 D02 LSB 0 D12 D10 D08 D06 D04 D02 LSB 0 MODE D0+A1 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1–A1 tLD MSB D11 D09 D07 D05 D03 D01 0 MSB D11 D09 D07 D05 D03 D01 0 D1+A1 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 FCO–1, FCO–2 FCO+1, FCO+2 D0–A1 BYTEWISE D05 D04 D03 D02 D01 LSB 0 0 D05 D04 D03 D02 D01 LSB 0 0 MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0+A1 D1–A1 MSB D12 D11 D10 D09 D08 D07 D06 MSB D12 D11 D10 D09 D08 D07 D06
003
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1+A1
1537- 1 Figure 3. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default) Rev. C | Page 8 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Enhancement Control (Register 0x0C) Output Mode (Register 0x14) Output Adjust (Register 0x15) Output Phase (Register 0x16) Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS BOARD LAYOUT CONSIDERATIONS Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock CLOCK STABILITY CONSIDERATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE