Datasheet AD9656 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | Quad, 16-Bit, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter |
| Seiten / Seite | 47 / 3 — AD9656. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 3/2017—Rev. 0 to … |
| Revision | A |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
AD9656. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 3/2017—Rev. 0 to Rev. A. 12/2013—Revision 0: Initial Version
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AD9656 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 21 Applications ... 1 Voltage Reference ... 23 General Description ... 1 Clock Input Considerations .. 24 Functional Block Diagram .. 1 Power Dissipation and Power-Down Mode ... 26 Product Highlights ... 1 Digital Outputs ... 26 Revision History ... 2 Serial Port Interface (SPI) .. 35 Specifications ... 3 Configuration Using the SPI ... 35 DC Specifications, VREF = 1.4 V .. 3 Hardware Interface ... 35 DC Specifications, VREF = 1.0 V .. 4 SPI Accessible Features .. 35 AC Specifications, VREF = 1.4 V .. 5 Memory Map .. 37 AC Specifications, VREF = 1.0 V .. 6 Reading the Memory Map Register Table ... 37 Digital Specifications ... 7 Memory Map Register Table ... 38 Switching Specifications .. 8 Memory Map Register Descriptions .. 42 Timing Specifications .. 9 Applications Information .. 44 Absolute Maximum Ratings .. 11 Design Guidelines .. 44 Thermal Resistance .. 11 Power and Ground Recommendations ... 44 ESD Caution .. 11 Clock Stability Considerations ... 44 Pin Configuration and Function Descriptions ... 12 Exposed Pad Thermal Heat Slug Recommendations .. 44 Typical Performance Characteristics ... 14 Reference Decoupling .. 44 VREF = 1.4 V ... 14 SPI Port .. 44 VREF = 1.0 V ... 17 Outline Dimensions ... 45 Equivalent Circuits ... 20 Ordering Guide .. 45 Theory of Operation .. 21
REVISION HISTORY 3/2017—Rev. 0 to Rev. A
Changes to Input Clock Divider Section ... 25 Changed DSYNC to SYNCINB, to SYSREF, DSYNC± to Changes to Power Dissipation and Power-Down Mode Section ... 26 SYNCINB±, and DSYSREF± to SYSREF± .. Throughout Change to JESD204B Transmit Top Level Description Section ... 26 Changes to Applications Section, General Description Section, and Added JESD204B Configurations Section Title, Initial JESD204B Product Highlights Section .. 1 Link Startup Section, and Figure 65 .. 27 Changes to Table 1 .. 3 Added Resynchronization Section and Figure 66 ... 28 Changes to Table 2 .. 4 Changes to CGS Phase Section and ILAS Phase Section .. 29 Changes to AC Specifications, VREF = 1.4 V Section and Table 3 .. 5 Added Figure 67 ... 29 Change to AC Specifications, VREF = 1.0 V Section ... 6 Change to Set Additional Digital Output Configuration Changes to Worst Other Spur or Harmonic (Excluding Second Options Section .. 31 or Third) Parameter, Table 4, Digital Specifications Section, Changes to Figure 68 and Figure 68 ... 32 and Table 5 ... 7 Changes to Digital Outputs and Timing Section and Figure 71 ... 33 Changes to Table 6 .. 8 Changes to Hardware Interface Section .. 35 Changes to Table 6 Endnotes .. 9 Changes to Table 19 ... 39 Changes to Figure 2 Caption ... 10 Change to Transfer (Register 0xFF) Section ... 42 Change to Table 8 ... 11 Changes to Resolution/Sample Rate Override (Register 0x100) .. 43 Changes to Table 10 .. 12 Changes to Power and Ground Recommendations Section and Changes to Figure 39, Figure 41, Figure 41 Caption, Clock Stability Considerations Section .. 44 and Figure 44 ... 20 Added Figure 42, Renumbered Sequentially .. 20
12/2013—Revision 0: Initial Version
Rev. A | Page 2 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS, VREF = 1.4 V DC SPECIFICATIONS, VREF = 1.0 V AC SPECIFICATIONS, VREF = 1.4 V AC SPECIFICATIONS, VREF = 1.0 V DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.4 V VREF = 1.0 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common-Mode Voltage Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS JESD204B Transmit Top Level Description JESD204B Overview JESD204B Configurations Initial JESD204B Link Startup Resynchronization JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bit 5—PDWN Pin Function Bit 4—JTX Standby Mode Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bit 2—Chop Mode Output Mode (Register 0x14) Bits[7:5]—JTX CS Mode Bits[1:0]—Output Format Clock Phase Control (Register 0x16) Bits[6:4]—Input Clock Phase Adjust JTX User Pattern (Register 0xA0 to Register 0xA7) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE
AD9656 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 21 Applications ... 1 Voltage Reference ... 23 General Description ... 1 Clock Input Considerations .. 24 Functional Block Diagram .. 1 Power Dissipation and Power-Down Mode ... 26 Product Highlights ... 1 Digital Outputs ... 26 Revision History ... 2 Serial Port Interface (SPI) .. 35 Specifications ... 3 Configuration Using the SPI ... 35 DC Specifications, VREF = 1.4 V .. 3 Hardware Interface ... 35 DC Specifications, VREF = 1.0 V .. 4 SPI Accessible Features .. 35 AC Specifications, VREF = 1.4 V .. 5 Memory Map .. 37 AC Specifications, VREF = 1.0 V .. 6 Reading the Memory Map Register Table ... 37 Digital Specifications ... 7 Memory Map Register Table ... 38 Switching Specifications .. 8 Memory Map Register Descriptions .. 42 Timing Specifications .. 9 Applications Information .. 44 Absolute Maximum Ratings .. 11 Design Guidelines .. 44 Thermal Resistance .. 11 Power and Ground Recommendations ... 44 ESD Caution .. 11 Clock Stability Considerations ... 44 Pin Configuration and Function Descriptions ... 12 Exposed Pad Thermal Heat Slug Recommendations .. 44 Typical Performance Characteristics ... 14 Reference Decoupling .. 44 VREF = 1.4 V ... 14 SPI Port .. 44 VREF = 1.0 V ... 17 Outline Dimensions ... 45 Equivalent Circuits ... 20 Ordering Guide .. 45 Theory of Operation .. 21
REVISION HISTORY 3/2017—Rev. 0 to Rev. A
Changes to Input Clock Divider Section ... 25 Changed DSYNC to SYNCINB, to SYSREF, DSYNC± to Changes to Power Dissipation and Power-Down Mode Section ... 26 SYNCINB±, and DSYSREF± to SYSREF± .. Throughout Change to JESD204B Transmit Top Level Description Section ... 26 Changes to Applications Section, General Description Section, and Added JESD204B Configurations Section Title, Initial JESD204B Product Highlights Section .. 1 Link Startup Section, and Figure 65 .. 27 Changes to Table 1 .. 3 Added Resynchronization Section and Figure 66 ... 28 Changes to Table 2 .. 4 Changes to CGS Phase Section and ILAS Phase Section .. 29 Changes to AC Specifications, VREF = 1.4 V Section and Table 3 .. 5 Added Figure 67 ... 29 Change to AC Specifications, VREF = 1.0 V Section ... 6 Change to Set Additional Digital Output Configuration Changes to Worst Other Spur or Harmonic (Excluding Second Options Section .. 31 or Third) Parameter, Table 4, Digital Specifications Section, Changes to Figure 68 and Figure 68 ... 32 and Table 5 ... 7 Changes to Digital Outputs and Timing Section and Figure 71 ... 33 Changes to Table 6 .. 8 Changes to Hardware Interface Section .. 35 Changes to Table 6 Endnotes .. 9 Changes to Table 19 ... 39 Changes to Figure 2 Caption ... 10 Change to Transfer (Register 0xFF) Section ... 42 Change to Table 8 ... 11 Changes to Resolution/Sample Rate Override (Register 0x100) .. 43 Changes to Table 10 .. 12 Changes to Power and Ground Recommendations Section and Changes to Figure 39, Figure 41, Figure 41 Caption, Clock Stability Considerations Section .. 44 and Figure 44 ... 20 Added Figure 42, Renumbered Sequentially .. 20
12/2013—Revision 0: Initial Version
Rev. A | Page 2 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS, VREF = 1.4 V DC SPECIFICATIONS, VREF = 1.0 V AC SPECIFICATIONS, VREF = 1.4 V AC SPECIFICATIONS, VREF = 1.0 V DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.4 V VREF = 1.0 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common-Mode Voltage Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS JESD204B Transmit Top Level Description JESD204B Overview JESD204B Configurations Initial JESD204B Link Startup Resynchronization JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bit 5—PDWN Pin Function Bit 4—JTX Standby Mode Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bit 2—Chop Mode Output Mode (Register 0x14) Bits[7:5]—JTX CS Mode Bits[1:0]—Output Format Clock Phase Control (Register 0x16) Bits[6:4]—Input Clock Phase Adjust JTX User Pattern (Register 0xA0 to Register 0xA7) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE