Datasheet AD7175-2 (Analog Devices) - 8

Data Sheet AD7175-2
Parameter Test Conditions/Comments Min Typ Max Unit
POWER DISSIPATION4 Full Operating Mode All buffers disabled, external clock and 21 mW reference, AVDD2 = 2 V, IOVDD = 2 V All buffers disabled, external clock and 42 mW reference, all supplies = 5 V All buffers disabled, external clock and 52 mW reference, all supplies = 5.5 V All buffers enabled, internal clock and 82 mW reference, AVDD2 = 2 V, IOVDD = 2 V All buffers enabled, internal clock and 105 mW reference, all supplies = 5 V All buffers enabled, internal clock and 136 mW reference, all supplies = 5.5 V Standby Mode Internal reference off, all supplies = 5 V 125 µW Internal reference on, all supplies = 5 V 2.2 mW Power-Down Mode Full power-down, all supplies = 5 V 25 50 µW 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification includes moisture sensitivity level (MSL) preconditioning effects. 4 This specification is with no load on the REFOUT and digital output pins.
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments1, 2
SCLK t3 25 ns min SCLK high pulse width t4 25 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 15 ns max IOVDD = 4.75 V to 5.5 V 40 ns max IOVDD = 2 V to 3.6 V t 3 2 0 ns min SCLK active edge to data valid delay4 12.5 ns max IOVDD = 4.75 V to 5.5 V 25 ns max IOVDD = 2 V to 3.6 V t 5 5 2.5 ns min Bus relinquish time after CS inactive edge 20 ns max t6 0 ns min SCLK inactive edge to CS inactive edge t7 10 ns min SCLK inactive edge to DOUT/RDY high/low WRITE OPERATION t8 0 ns min CS falling edge to SCLK active edge setup time4 t9 8 ns min Data valid to SCLK edge setup time t10 8 ns min Data valid to SCLK edge hold time t11 5 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. Rev. B | Page 7 of 62