Datasheet AD7175-2 (Analog Devices) - 6

HerstellerAnalog Devices
Beschreibung24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers
Seiten / Seite63 / 6 — Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
RevisionB
Dateiformat / GrößePDF / 1.1 Mb
DokumentenspracheEnglisch

Parameter. Test Conditions/Comments. Min. Typ. Max. Unit

Parameter Test Conditions/Comments Min Typ Max Unit

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Data Sheet AD7175-2
Parameter Test Conditions/Comments Min Typ Max Unit
Turn-On Settling Time 100 nF REFOUT capacitor 200 µs Short-Circuit Current, ISC 25 mA EXTERNAL REFERENCE INPUTS Differential Input Range VREF = (REF+) − (REF−) 1 2.5 AVDD1 V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V REFIN Input Current Input Buffers Disabled Input Current ±72 µA/V Input Current Drift External clock ±1.2 nA/V/°C Internal clock ±6 nA/V/°C Input Buffers Enabled Input Current ±800 nA Input Current Drift 1.25 nA/°C Normal Mode Rejection1 See the Rejection parameter Common-Mode Rejection 95 dB TEMPERATURE SENSOR Accuracy After user calibration at 25°C ±2 °C Sensitivity 470 µV/K BURNOUT CURRENTS Source/Sink Current Analog input buffers must be enabled ±10 µA GENERAL-PURPOSE INPUT/ With respect to AVSS OUTPUT (GPIO0, GPIO1) Input Mode Leakage Current1 −10 +10 µA Floating State Output 5 pF Capacitance Output High Voltage, V 1 OH ISOURCE = 200 µA AVSS + 4 V Output Low Voltage, V 1 OL ISINK = 800 µA AVSS + 0.4 V Input High Voltage, V 1 IH AVSS + 3 V Input Low Voltage, V 1 IL AVSS + 0.7 V CLOCK Internal Clock Frequency 16 MHz Accuracy −2.5% +2.5% % Duty Cycle 50 % Output Low Voltage, VOL 0.4 V Output High Voltage, VOH 0.8 × IOVDD V Crystal Frequency 14 16 16.384 MHz Startup Time 10 µs External Clock (CLKIO) 16 16.384 MHz Duty Cycle1 30 50 70 % Rev. B | Page 5 of 62