Datasheet HMCAD5831LP9BE (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 26 GS/s 3-Bit Analog-to-Digital Converter w/ Overrange, Inhibit, and 1:2 DEMUX |
| Seiten / Seite | 15 / 9 — HMCAD5831LP9BE. 3-BIT 26 GSPS ANALOG-TO-DIGITAL. CONVERTER W/ OVERRANGE, … |
| Dateiformat / Größe | PDF / 939 Kb |
| Dokumentensprache | Englisch |
HMCAD5831LP9BE. 3-BIT 26 GSPS ANALOG-TO-DIGITAL. CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX. Pin Descriptions
Modelllinie für dieses Datenblatt
Textversion des Dokuments
HMCAD5831LP9BE
v02.0713
3-BIT 26 GSPS ANALOG-TO-DIGITAL CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX Pin Descriptions
Pin number Function Description Interface schematic 1, 15 rtF, rBF reference ladder top and bottom taps t 2, 7, 9, 10, 13, M 16, 17, 18, 21, aGnD analog ground 60, 63, 64 s -5v analog rail 3, 4, 5, 6, 14 avee these pins and the exposed paddle must be connected s - to the negative voltage supply. r e t 8 In single-ended rF input referenced to aGnD. r e v n Differential clock inputs o Current Mode Logic (CML) referenced to aGnD. 11, 12 CKP, CKn For single-ended operation, CKn must be tied to the common-mode point. ata C D Differential Xor inputs 19, 20 XorP, Xorn Current Mode Logic (CML) referenced to aGnD. For single-ended operation, Xorn must be tied to the common-mode point. 22, 23, 27, 30, 33, 36, 39, 42, oGnD Digital ground 45, 48, 51, 54, 58, 59 24, 25, 56, 57 ovee -3.3v digital rail output level control 26, 55 vreF2, vreF1 output level may be increased or decreased by applying a voltage to vref pins. overrange Xvn, XvP, Yvn, 28, 29, 31, 32 Current Mode Logic (CML) referenced to oGnD. YvP normally ac-coupled to the digital asIC or FPGa device. X0n, X0P, Y0n, 34, 35, 37, 38, Differential data outputs Y0P, X1n, X1P, 43, 44, 46, 47, Current Mode Logic (CML) referenced to oGnD. Y1n, Y1P, X2n, 49, 50, 52, 53 normally ac-coupled to the digital asIC or FPGa device. X2P, Y2n, Y2P Differential clock output 40, 41 oCLKn, oCLKP Current Mode Logic (CML) referenced to oGnD. Differential data inhibit inputs 61, 62 Qtn, QtP For single-ended operation, Qtn must be tied to the common-mode point. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com
8
Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 pp3li o ca rti a o pp n Susp@h portitti : P te ho .c neom : 1-800-ANALOG-D
v02.0713
3-BIT 26 GSPS ANALOG-TO-DIGITAL CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX Pin Descriptions
Pin number Function Description Interface schematic 1, 15 rtF, rBF reference ladder top and bottom taps t 2, 7, 9, 10, 13, M 16, 17, 18, 21, aGnD analog ground 60, 63, 64 s -5v analog rail 3, 4, 5, 6, 14 avee these pins and the exposed paddle must be connected s - to the negative voltage supply. r e t 8 In single-ended rF input referenced to aGnD. r e v n Differential clock inputs o Current Mode Logic (CML) referenced to aGnD. 11, 12 CKP, CKn For single-ended operation, CKn must be tied to the common-mode point. ata C D Differential Xor inputs 19, 20 XorP, Xorn Current Mode Logic (CML) referenced to aGnD. For single-ended operation, Xorn must be tied to the common-mode point. 22, 23, 27, 30, 33, 36, 39, 42, oGnD Digital ground 45, 48, 51, 54, 58, 59 24, 25, 56, 57 ovee -3.3v digital rail output level control 26, 55 vreF2, vreF1 output level may be increased or decreased by applying a voltage to vref pins. overrange Xvn, XvP, Yvn, 28, 29, 31, 32 Current Mode Logic (CML) referenced to oGnD. YvP normally ac-coupled to the digital asIC or FPGa device. X0n, X0P, Y0n, 34, 35, 37, 38, Differential data outputs Y0P, X1n, X1P, 43, 44, 46, 47, Current Mode Logic (CML) referenced to oGnD. Y1n, Y1P, X2n, 49, 50, 52, 53 normally ac-coupled to the digital asIC or FPGa device. X2P, Y2n, Y2P Differential clock output 40, 41 oCLKn, oCLKP Current Mode Logic (CML) referenced to oGnD. Differential data inhibit inputs 61, 62 Qtn, QtP For single-ended operation, Qtn must be tied to the common-mode point. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com
8
Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 pp3li o ca rti a o pp n Susp@h portitti : P te ho .c neom : 1-800-ANALOG-D