Datasheet AD7172-2 (Analog Devices) - 7

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AD7172-2 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 1 OH IOVDD ≥ 4.5 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA 0.8 × IOVDD V IOVDD < 2.7 V, ISOURCE = 200 µA 0.8 × IOVDD V Output Low Voltage, V 1 OL IOVDD ≥ 4.5 V, ISINK = 2 mA 0.4 V 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA 0.4 V IOVDD < 2.7 V, ISINK = 400 µA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION1 Full-Scale (FS) Calibration 1.05 × FS V Limit Zero-Scale Calibration Limit −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER REQUIREMENTS Power Supply Voltage AVDD1 to AVSS 3.0 5.5 V AVDD2 to AVSS 2 5.5 V AVSS to DGND −2.75 0 V IOVDD to DGND 2 5.5 V IOVDD to AVSS For AVSS < DGND 6.35 V POWER SUPPLY CURRENTS4 All outputs unloaded, digital inputs connected to IOVDD or DGND Full Operating Mode AVDD1 Current AVDD1 = 5 V Typical, AIN± and REF± buffers disabled; external 0.23 0.27 mA 5.5 V Maximum reference AIN± and REF± buffers disabled; internal 0.4 0.48 mA reference AIN± and REF± buffers enabled; internal 1.9 2.35 mA reference Each buffer: AIN± and REF± 0.38 mA AVDD1 = 3.3 V Typical, AIN± and REF± buffers disabled; external 0.15 0.19 mA 3.6 V Maximum1 reference AIN± and REF± buffers disabled; internal 0.33 0.39 mA reference AIN± and REF± buffers enabled; internal 1.65 2.1 mA reference Each buffer: AIN± and REF± 0.33 mA AVDD2 Current External reference 1 1.1 mA Internal reference 1.3 1.45 mA IOVDD Current External clock 0.33 0.5 mA Internal clock 0.61 0.82 mA External crystal 0.98 mA Standby Mode Standby (LDO On) Reference off, total current consumption 32 µA Reference on, total current consumption 420 µA Power-Down Mode Full power-down, LDO, REF± 1 10 µA Rev. A | Page 6 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE