Datasheet AD9684 (Analog Devices) - 4

HerstellerAnalog Devices
Beschreibung14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter
Seiten / Seite65 / 4 — Data Sheet. AD9684. PRODUCT HIGHLIGHTS
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DokumentenspracheEnglisch

Data Sheet. AD9684. PRODUCT HIGHLIGHTS

Data Sheet AD9684 PRODUCT HIGHLIGHTS

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Data Sheet AD9684
The AD9684 has several functions that simplify the automatic The AD9684 has flexible power-down options that allow gain control (AGC) function in a communications receiver. The significant power savings when desired. All of these features can programmable threshold detector allows monitoring of the be programmed using a 1.8 V to 3.4 V capable 3-wire serial port incoming signal power using the fast detect output bits of the interface (SPI). ADC. If the input signal level exceeds the programmable The AD9684 is available in a Pb-free, 196-bal ball grid array threshold, the fast detect indicator goes high. Because this (BGA) and is specified over the −40°C to +85°C industrial threshold indicator has low latency, the user can quickly reduce temperature range. This product is protected by a U.S. patent. the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9684 also
PRODUCT HIGHLIGHTS
offers signal monitoring capability. The signal monitoring block 1. Wide ful power bandwidth supports intermediate provides additional information about the signal that the ADC frequency (IF) sampling of signals up to 2 GHz. digitized. 2. Buffered inputs with programmable input termination ease The dual ADC output data is routed directly to the one external, filter design and implementation. 14-bit LVDS output port, supporting double data rate (DDR) 3. Four integrated wideband decimation filters and NCO formatting. An external data clock and status bit are offered for blocks supporting multiband receivers. data capture flexibility. 4. Flexible SPI controls various product features and functions to meet specific system requirements. The LVDS outputs have several configurations, depending on 5. Programmable fast overrange detection and signal the acceptable rate of the receiving logic device and the sampling monitoring. rate of the ADC. Multiple device synchronization is supported 6. SYNC± input allows synchronization of multiple devices. through the SYNC± input pins. 7. 12 mm × 12 mm, 196-ball BGA_ED. Rev. 0 | Page 3 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE