Datasheet AD7124-4 (Analog Devices) - 9

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AD7124-4 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments
EXCITATION CURRENT SOURCES (IOUT0/IOUT1) Available on any analog input pin Output Current 50/100/250/ µA 500/750/1000 Initial Tolerance ±4 % TA = 25°C Drift 50 ppm/°C Current Matching ±0.5 % Matching between IOUT0 and IOUT1, VOUT = 0 V Drift Matching2 5 30 ppm/°C Line Regulation (AVDD) 2 %/V AVDD = 3 V ± 5% Load Regulation 0.2 %/V Output Compliance2 AVSS − 0.05 AVDD − 0.37 V 50 µA/100 µA/250 µA/500 µA current sources, 2% accuracy AVSS − 0.05 AVDD − 0.48 V 750 µA and 1000 µA current sources, 2% accuracy BIAS VOLTAGE (VBIAS) GENERATOR Available on any analog input pin VBIAS AVSS + (AVDD − V AVSS)/2 VBIAS Generator Start-Up Time 6.7 µs/nF Dependent on the capacitance connected to AINx TEMPERATURE SENSOR Accuracy ±0.5 °C Sensitivity 13,584 Codes/°C LOW-SIDE POWER SWITCH On Resistance (RON) 7 10 Ω Allowable Current2 30 mA Continuous current BURNOUT CURRENTS AIN Current 0.5/2/4 µA Analog inputs must be buffered DIGITAL OUTPUTS (P1 AND P2) Output Voltage High, VOH AVDD − 0.6 V ISOURCE = 100 µA Low, VOL 0.4 V ISINK = 100 µA DIAGNOSTICS Power Supply Monitor Detect Level Analog Low Dropout Regulator (ALDO) 1.6 V AVDD − AVSS ≥ 2.7 V Digital LDO (DLDO) 1.55 V IOVDD ≥ 1.75 V Reference Detect Level 0.7 1 V REF_DET_ERR bit active if VREF < 0.7 V AINM/AINP Overvoltage Detect Level AVDD + 0.04 V AINM/AINP Undervoltage Detect Level AVSS − 0.04 V INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 614.4 − 5% 614.4 614.4 + 5% kHz Duty Cycle 50:50 % External Clock Frequency 2.4576 MHz Internal divide by 4 Duty Cycle Range 45:55 to 55:45 % LOGIC INPUTS2 Input Voltage Low, VINL 0.3 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.35 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 0.7 V 2.3 V ≤ IOVDD ≤ 3.6 V High, VINH 0.7 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.65 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 1.7 V 2.3 V ≤ IOVDD < 2.7 V 2 V 2.7 V ≤ IOVDD ≤ 3.6 V Hysteresis 0.2 0.6 V 1.65 V ≤ IOVDD ≤ 3.6 V Input Currents −1 +1 µA VIN = IOVDD or GND Input Capacitance 10 pF All digital inputs Rev. C | Page 8 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE