Datasheet AD7124-4 (Analog Devices) - 7

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AD7124-4 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments
Fast Settling Filters2 At 50 Hz 115 dB First notch at 50 Hz, 50 Hz ± 1 Hz At 60 Hz 115 dB First notch at 60 Hz, 60 Hz ± 1 Hz Post Filters2 At 50 Hz, 60 Hz 130 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 130 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Normal Mode Rejection2 Sinc4 Filter External Clock At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 80 dB 50 SPS, REJ6010=1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz Internal Clock At 50 Hz, 60 Hz 98 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 66 dB 50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 92 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 92 dB 60 SPS, 60 Hz ± 1 Hz Sinc3 Filter External Clock At 50 Hz, 60 Hz 100 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 65 dB 50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 100 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 100 dB 60 SPS, 60 Hz ± 1 Hz Internal Clock At 50 Hz, 60 Hz 73 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 52 dB 50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 68 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 68 dB 60 SPS, 60 Hz ± 1 Hz Fast Settling Filters External Clock At 50 Hz 40 dB First notch at 50 Hz, 50 Hz ± 0.5 Hz At 60 Hz 40 dB First notch at 60 Hz, 60 Hz ± 0.5 Hz Internal Clock At 50 Hz 24.5 dB First notch at 50 Hz, 50 Hz ± 0.5 Hz At 60 Hz 24.5 dB First notch at 60 Hz, 60 Hz ± 0.5 Hz Post Filters External Clock At 50 Hz, 60 Hz 86 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 62 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Internal Clock At 50 Hz, 60 Hz 67 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz ANALOG INPUTS11 Differential Input Voltage Ranges12 ±VREF/gain V VREF = REFINx(+) − REFINx(−), or internal reference Absolute AIN Voltage Limits2 Gain = 1 (Unbuffered) AVSS − 0.05 AVDD + 0.05 V Gain = 1 (Buffered) AVSS + 0.1 AVDD − 0.1 V Gain > 1 AVSS − 0.05 AVDD + 0.05 V Rev. C | Page 6 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE