Datasheet AD7124-4 (Analog Devices) - 5

AD7124-4 Data Sheet GENERAL DESCRIPTION
The AD7124-4 is a low power, low noise, completely integrated The integrated channel sequencer allows several channels to be analog front end for high precision measurement applications. enabled simultaneously, and the AD7124-4 sequentially converts The device contains a low noise, 24-bit Σ-Δ analog-to-digital on each enabled channel, simplifying communication with the converter (ADC), and can be configured to have four differential device. As many as 16 channels can be enabled at any time; a inputs or seven single-ended or pseudo differential inputs. The channel being defined as an analog input or a diagnostic such on-chip low gain stage ensures that signals of small amplitude as a power supply check or a reference check. This unique can be interfaced directly to the ADC. feature allows diagnostics to be interleaved with conversions. One of the major advantages of the AD7124-4 is that it gives the The AD7124-4 also supports per channel configuration. The user the flexibility to employ one of three integrated power device allows eight configurations or setups. Each configuration modes. The current consumption, range of output data rates, consists of gain, filter type, output data rate, buffering, and and rms noise can be tailored with the power mode selected. reference source. The user can assign any of these setups on a The device also offers a multitude of filter options, ensuring that channel by channel basis. the user has the highest degree of flexibility. The AD7124-4 also has extensive diagnostic functionality The AD7124-4 can achieve simultaneous 50 Hz and 60 Hz integrated as part of its comprehensive feature set. These rejection when operating at an output data rate of 25 SPS (single diagnostics include a cyclic redundancy check (CRC), signal cycle settling), with rejection in excess of 80 dB achieved at lower chain checks, and serial interface checks, which lead to a more output data rates. robust solution. These diagnostics reduce the need for external components to implement diagnostics, resulting in reduced The AD7124-4 establishes the highest degree of signal chain board space needs, reduced design cycle times, and cost savings. integration. The device contains a precision, low noise, low The failure modes effects and diagnostic analysis (FMEDA) of a drift internal band gap reference, and also accepts an external typical application has shown a safe failure fraction (SFF) greater differential reference, which can be internally buffered. Other than 90% according to IEC 61508. key integrated features include programmable low drift excitation current sources, burnout currents, and a bias voltage generator, The device operates with a single analog power supply from 2.7 V which sets the common-mode voltage of a channel to AV to 3.6 V or a dual 1.8 V power supply. The digital supply has a DD/2. The low-side power switch enables the user to power down range of 1.65 V to 3.6 V. It is specified for a temperature range bridge sensors between conversions, ensuring the absolute of −40°C to +125°C. The AD7124-4 is housed in a 32-lead minimal power consumption of the system. The device also LFCSP package and a 24-lead TSSOP package. allows the user the option of operating with either an internal Note that, throughout this data sheet, multifunction pins, such clock or an external clock. as DOUT/RDY, are referred to either by the entire pin name or by a single function of the pin, for example, RDY, when only that function is relevant.
Table 1. AD7124-4 Ov erview Parameter Low Power Mode Mid Power Mode Full Power Mode
Maximum Output Data Rate 2400 SPS 4800 SPS 19,200 SPS RMS Noise (Gain = 128) 24 nV 20 nV 23 nV Peak-to-Peak Resolution at 1200 SPS 16.4 bits 17.1 bits 18 bits (Gain = 1) Typical Current (ADC + PGA) 255 µA 355 µA 930 µA Rev. C | Page 4 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE