Datasheet AD7761 (Analog Devices) - 7

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AD7761 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
EXTERNAL REFERENCE Reference Voltage VREF = (REFx+) − (REFx−) 1 AVDD1 − AVSS V Absolute Reference Voltage Limits2 Precharge reference buffers off AVSS − AVDD1 + 0.05 V 0.05 Precharge reference buffers on AVSS AVDD1 V Average Reference Current Fast mode Precharge reference buffers off ±72 µA/V/channel Precharge reference buffers on ±16 µA/V/channel Average Reference Current Drift Fast mode Precharge reference buffers off ±1.7 nA/V/°C Precharge reference buffers on ±49 nA/V/°C Common-Mode Rejection 95 dB DIGITAL FILTER RESPONSE Low Ripple Wideband Filter FILTER = 0 Decimation Rate Up to six selectable decimation rates 32 1024 Group Delay Latency 34/ODR sec Settling Time Complete settling 68/ODR sec Pass-Band Ripple2 ±0.005 dB Pass Band ±0.005 dB bandwidth 0.4 × ODR Hz −0.1 dB bandwidth 0.409 × ODR Hz −3 dB bandwidth 0.433 × ODR Hz Stop Band Frequency Attenuation > 105 dB 0.499 × ODR Hz Stop Band Attenuation 105 dB Sinc5 Filter FILTER = 1 Decimation Rate Up to six selectable decimation rates 32 1024 Group Delay Latency 3/ODR sec Settling Time Complete settling 7/ODR sec Pass Band −3 dB bandwidth 0.204 × ODR Hz REJECTION AC Power Supply Rejection Ratio VIN = 0.1 V, AVDD1 = 5 V, AVDD2 = (PSRR) 5 V, IOVDD = 2.5 V AVDD1 90 dB AVDD2 100 dB IOVDD 75 dB DC PSRR VIN = 1 V AVDD1 100 dB AVDD2 118 dB IOVDD 90 dB Analog Input Common-Mode Rejection Ratio (CMRR) DC VIN = 0.1 V 95 dB AC Up to 10 kHz 95 dB Crosstalk −0.5 dBFS input on adjacent channels −120 dB CLOCK See the Clock Selection section for data sheet performance functionality Crystal Frequency 8 32.768 34 MHz External Clock (MCLK) 32.768 MHz Duty Cycle 50:50 % MCLK Pulse Width2 Logic Low 12.2 ns Logic High 12.2 ns CMOS Clock Input Voltage See the Logic Inputs parameter High, VINH Low, VINL Rev. A | Page 6 of 75 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE