Datasheet AD7761 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW |
| Seiten / Seite | 76 / 3 — AD7761. Data Sheet. TABLE OF CONTENTS |
| Revision | A |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
AD7761. Data Sheet. TABLE OF CONTENTS
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AD7761 Data Sheet TABLE OF CONTENTS
Features .. 1 Setting the Format of Data Output .. 49 Applications ... 1 ADC Conversion Output: Header and Data .. 50 Functional Block Diagram .. 1 Functionality ... 59 Revision History ... 3 GPIO Functionality .. 59 General Description ... 4 Register Map Details (SPI Control) ... 60 Specifications ... 5 Register Map ... 60 Timing Specifications .. 10 Channel Standby Register ... 62 1.8 V IOVDD Timing Specifications ... 11 Channel Mode A Register ... 63 Absolute Maximum Ratings .. 15 Channel Mode B Register ... 63 Thermal Resistance .. 15 Channel Mode Select Register .. 64 ESD Caution .. 15 Power Mode Select Register .. 64 Pin Configuration and Function Descriptions ... 16 General Device Configuration Register .. 65 Typical Performance Characteristics ... 20 Data Control: Soft Reset, Sync, and Single-Shot Control Terminology .. 26 Register .. 66 Theory of Operation .. 27 Interface Configuration Register .. 66 Clocking, Sampling Tree, and Power Scaling ... 27 Digital Filter RAM Built in Self Test (BIST) Register .. 67 Noise Performance and Resolution .. 28 Status Register ... 67 Applications Information .. 30 Revision Identification Register ... 68 Power Supplies .. 31 GPIO Control Register .. 68 Device Configuration .. 32 GPIO Write Data Register ... 69 Pin Control Mode ... 32 GPIO Read Data Register .. 69 SPI Control .. 35 Analog Input Precharge Buffer Enable Register Channel 0 to Channel 3 .. 69 SPI Control Functionality ... 36 Analog Input Precharge Buffer Enable Register Channel 4 to SPI Control Mode Extra Diagnostic Features .. 38 Channel 7 .. 70 Circuit Information .. 39 Positive Reference Precharge Buffer Enable Register .. 70 Core Signal Chain ... 39 Negative Reference Precharge Buffer Enable Register .. 71 Analog Inputs .. 40 Offset Registers ... 71 VCM ... 41 Gain Registers ... 72 Reference Input ... 42 Sync Phase Offset Registers .. 72 Clock Selection ... 42 ADC Diagnostic Receive Select Register .. 72 Digital Filtering ... 42 ADC Diagnostic Control Register ... 73 Decimation Rate Control .. 46 Modulator Delay Control Register ... 74 Antialiasing ... 46 Chopping Control Register ... 74 Calibration ... 48 Outline Dimensions ... 75 Data Interface .. 49 Ordering Guide .. 75 Rev. A | Page 2 of 75 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
AD7761 Data Sheet TABLE OF CONTENTS
Features .. 1 Setting the Format of Data Output .. 49 Applications ... 1 ADC Conversion Output: Header and Data .. 50 Functional Block Diagram .. 1 Functionality ... 59 Revision History ... 3 GPIO Functionality .. 59 General Description ... 4 Register Map Details (SPI Control) ... 60 Specifications ... 5 Register Map ... 60 Timing Specifications .. 10 Channel Standby Register ... 62 1.8 V IOVDD Timing Specifications ... 11 Channel Mode A Register ... 63 Absolute Maximum Ratings .. 15 Channel Mode B Register ... 63 Thermal Resistance .. 15 Channel Mode Select Register .. 64 ESD Caution .. 15 Power Mode Select Register .. 64 Pin Configuration and Function Descriptions ... 16 General Device Configuration Register .. 65 Typical Performance Characteristics ... 20 Data Control: Soft Reset, Sync, and Single-Shot Control Terminology .. 26 Register .. 66 Theory of Operation .. 27 Interface Configuration Register .. 66 Clocking, Sampling Tree, and Power Scaling ... 27 Digital Filter RAM Built in Self Test (BIST) Register .. 67 Noise Performance and Resolution .. 28 Status Register ... 67 Applications Information .. 30 Revision Identification Register ... 68 Power Supplies .. 31 GPIO Control Register .. 68 Device Configuration .. 32 GPIO Write Data Register ... 69 Pin Control Mode ... 32 GPIO Read Data Register .. 69 SPI Control .. 35 Analog Input Precharge Buffer Enable Register Channel 0 to Channel 3 .. 69 SPI Control Functionality ... 36 Analog Input Precharge Buffer Enable Register Channel 4 to SPI Control Mode Extra Diagnostic Features .. 38 Channel 7 .. 70 Circuit Information .. 39 Positive Reference Precharge Buffer Enable Register .. 70 Core Signal Chain ... 39 Negative Reference Precharge Buffer Enable Register .. 71 Analog Inputs .. 40 Offset Registers ... 71 VCM ... 41 Gain Registers ... 72 Reference Input ... 42 Sync Phase Offset Registers .. 72 Clock Selection ... 42 ADC Diagnostic Receive Select Register .. 72 Digital Filtering ... 42 ADC Diagnostic Control Register ... 73 Decimation Rate Control .. 46 Modulator Delay Control Register ... 74 Antialiasing ... 46 Chopping Control Register ... 74 Calibration ... 48 Outline Dimensions ... 75 Data Interface .. 49 Ordering Guide .. 75 Rev. A | Page 2 of 75 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE