Datasheet AD9694 (Analog Devices) - 7

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AD9694 Data Sheet Analog Input Full Scale = Analog Input Full Scale = Analog Input Full Scale = 1.44 V p-p 1.80 V p-p 2.16 V p-p Parameter1 Min Typ Max Min Typ Max Min Typ Max Unit
WORST HARMONIC, SECOND OR THIRD AT −3 dBFS fIN = 10 MHz −94 −94 −86 dBFS fIN = 155 MHz −94 −90 −82 dBFS fIN = 305 MHz −89 −90 −83 dBFS fIN = 450 MHz −87 −86 −84 dBFS fIN = 765 MHz −82 −80 −77 dBFS fIN = 985 MHz −85 −82 −79 dBFS WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC2 fIN = 10 MHz −96 −98 −99 dBFS fIN = 155 MHz −97 −97 −86 −97 dBFS fIN = 305 MHz −97 −98 −97 dBFS fIN = 450 MHz −95 −96 −96 dBFS fIN = 765 MHz −92 −91 −88 dBFS fIN = 985 MHz −90 −89 −86 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2= −7 dBFS fIN1 = 154 MHz, fIN2 = 157 MHz −93 −90 −84 dBFS fIN1 = 302 MHz, fIN2 = 305 MHz −90 −90 −84 dBFS CROSSTALK4 82 82 82 dB FULL POWER BANDWIDTH5 1.4 1.4 1.4 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 11 for recommended settings for full-scale voltage and buffer current setting. 4 Crosstalk is measured at 155 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with circuit shown in Figure 56.
Table 3. 600 M SPS AC Specifications, Analog Input = 1.80 V p-p Parameter1 Min Typ Max Unit
ANALOG INPUT FULL SCALE 1.80 V p-p SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz 66.6 dBFS fIN = 155 MHz 67 dBFS fIN = 305 MHz 66.8 dBFS fIN = 450 MHz 66.4 dBFS fIN = 765 MHz 66 dBFS fIN = 985 MHz 65.5 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 10 MHz 66.5 dBFS fIN = 155 MHz 66.8 dBFS fIN = 305 MHz 66.5 dBFS fIN = 450 MHz 66.3 dBFS fIN = 765 MHz 65.4 dBFS fIN = 985 MHz 64.8 dBFS SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz 86 dBFS fIN = 155 MHz 81 dBFS fIN = 305 MHz 81 dBFS fIN = 450 MHz 84 dBFS fIN = 765 MHz 76 dBFS fIN = 985 MHz 75 dBFS Rev. 0 | Page 6 of 101 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Dither Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C, AND FD_D) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO AND MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS OVERVIEW HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE SETTING UP THE AD9694 DIGITAL INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) LATENCY END-TO-END TOTAL LATENCY MULTICHIP SYNCHRONIZATION SYSREF± SET UP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels ADC Pair Addressing Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE SUMMARY MEMORY MAP REGISTER TABLE—DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) OUTLINE DIMENSIONS ORDERING GUIDE