Datasheet AD4020 (Analog Devices) - 7

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AD4020 Data Sheet TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled (fS = 1.8 MSPS), unless otherwise noted. See Figure 2 for the timing voltage levels.
Table 2. Digital Interface Timing Parameter Symbol Min Typ Max Unit
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE tCONV 300 320 350 ns ACQUISITION PHASE1 tACQ 325 ns TIME BETWEEN CONVERSIONS tCYC 555 ns CNV PULSE WIDTH (CS MODE)2 tCNVH 10 ns SCK PERIOD tSCK CS Mode3 VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns Daisy-Chain Mode4 VIO > 2.7 V 20 ns VIO > 1.7 V 25 ns SCK LOW TIME tSCKL 3 ns SCK HIGH TIME tSCKH 3 ns SCK FALLING EDGE TO DATA REMAINS VALID DELAY tHSDO 1.5 ns SCK FALLING EDGE TO DATA VALID DELAY tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV OR SDI LOW TO SDO D17 MSB VALID DELAY (CS MODE) tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 200 ns LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY5 tQUIET2 60 ns CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tDIS 20 ns SDI VALID SETUP TIME FROM CNV RISING EDGE tSSDICNV 2 ns SDI VALID HOLD TIME FROM CNV RISING EDGE CS Mode tHSDICNV 2 ns Daisy-Chain Mode tHSCKCNV 12 ns SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tSSDISCK 2 ns SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSDISCK 2 ns 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1.8 MSPS. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 1.8 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 71 MHz. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD vs. tQUIET2.
Y% VIO1 X% VIO1 tDELAY tDELAY V 2 V 2 IH IH 2 V 2 VIL IL 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30. 2
002
MINIMUM VIH AND MAXIMUM VIL USED. SEE THE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1.
15369- Figure 2. Voltage Levels for Timing Rev. A | Page 6 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Differential Input Considerations Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE Single to Differential Driver High Frequency Input Signals Multiplexed Applications EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD /CS MODE, 3-WIRE TURBO MODE /CS MODE, 3-WIRE WITHOUT THE BUSY INDICATOR /CS MODE, 3-WIRE WITH THE BUSY INDICATOR /CS MODE, 4-WIRE TURBO MODE /CS MODE, 4-WIRE WITHOUT THE BUSY INDICATOR /CS MODE, 4-WIRE WITH THE BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4020 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE