Datasheet AD7616-P (Analog Devices)

16-Channel DAS with 16-Bit, Bipolar Input, Dual Simultaneous Sampling ADC Data Sheet AD7616-P FEATURES APPLICATIONS 16-channel, dual, simultaneously sampled inputs Power line monitoring Independently selectable channel input ranges Protective relays True bipolar: ±10 V, ±5 V, ±2.5 V Multiphase motor control Single 5 V analog supply and 2.3 V to 3.6 V V supply Instrumentation and control systems DRIVE Fully integrated data acquisition solution Data acquisition systems (DASs) Analog input clamp protection GENERAL DESCRIPTION Input buffer with 1 MΩ analog input impedance 1st-order antialiasing analog filter
The AD7616-P is a 16-bit, DAS that supports dual simultaneous
On-chip accurate reference and reference buffer
sampling of 16 channels. The AD7616-P operates from a single
Dual 16-bit SAR ADC
5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true
Throughput rate: 2 × 1 MSPS
bipolar input signals while sampling at throughput rates up to
Oversampling capability with digital filter
1 MSPS per channel pair with 90.5 dB SNR. Higher signal-to-
Flexible sequencer with burst mode
noise ratio (SNR) performance can be achieved with the on-chip
Parallel digital interface
oversampling mode (92 dB for an oversampling ratio (OSR) of 2).
Optional CRC error checking
The input clamp protection circuitry tolerates voltages up to
Hardware/software configuration
±21 V. The AD7616-P has 1 MΩ analog input impedance,
Performance
regardless of sampling frequency. The single-supply operation,
92 dB SNR at 500 kSPS (2× OSR)
on-chip filtering, and high input impedance eliminate the need
90.5 dB SNR at 1 MSPS
for driver op amps and external bipolar supplies.
−103 dB THD
The device contains analog input clamp protection, a dual, 16-bit
±1 LSB INL (typical), ±0.99 LSB DNL (maximum)
charge redistribution successive approximation register (SAR)
8 kV ESD rating on analog input pins
analog-to-digital converter (ADC), a flexible digital filter, a
On-chip self detect function
2.5 V reference and reference buffer, and a high speed paral el
80-lead LQFP package
interface.
FUNCTIONAL BLOCK DIAGRAM VCC REFCAP REFINOUT REFSEL REGCAP REGCAPD VDRIVE 1MΩ R V0A CLAMP FB 2.5V 1.8V 1.8V REF ALDO DLDO FIRST- V0AGND CLAMP ORDER LPF 1MΩ RFB 9:1 MUX 1MΩ R V7A CLAMP FB PAR 16-BIT FIRST- V7AGND CLAMP PARALLEL ORDER LPF SAR OSR 1MΩ R INTERFACE FB DIGITAL PARALLEL DB15 TO DB0 FILTER 16-BIT 1MΩ RFB V0B CLAMP SAR FIRST- V0BGND CLAMP ORDER LPF 1MΩ RFB 9:1 MUX 1MΩ RFB RESET V7B CLAMP FIRST- FLEXIBLE WR/BURST V7BGND CLAMP ORDER LPF SEQUENCER SEQEN 1MΩ RFB CONTROL HW_RNGSEL0, HW_RNGSEL1 INPUTS CHSEL2 TO CHSEL0 VCC 2:1 CLK OSC AD7616-P BUSY MUX ALDO CONVST
001
AGND DGND
15695- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Universal Timing Specifications Parallel Interface Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Channel Selection Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE SHUTDOWN MODE DIGITAL FILTER APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW POWER SUPPLIES TYPICAL CONNECTIONS DEVICE CONFIGURATION OPERATIONAL MODE INTERNAL/EXTERNAL REFERENCE HARDWARE MODE SOFTWARE MODE RESET FUNCTIONALITY PIN FUNCTION OVERVIEW DIGITAL INTERFACE CHANNEL SELECTION Hardware Mode Software Mode PARALLEL INTERFACE Reading Conversion Results Writing Register Data Reading Register Data SEQUENCER HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER BURST SEQUENCER Hardware Mode Burst Software Mode Burst DIAGNOSTICS DIAGNOSTIC CHANNELS INTERFACE SELF TEST CRC REGISTER SUMMARY ADDRESSING REGISTERS CONFIGURATION REGISTER CHANNEL REGISTER INPUT RANGE REGISTERS Input Range Register A1 Input Range Register A2 Input Range Register B1 Input Range Register B2 SEQUENCER STACK REGISTERS Sequencer Stack Register 0 to Sequencer Stack Register 7 Sequencer Stack Register 8 to Sequencer Stack Register 31 STATUS REGISTER OUTLINE DIMENSIONS ORDERING GUIDE