Datasheet LT3519, LT3519-1, LT3519-2 (Analog Devices) - 6

LT3519/LT3519-1/LT3519-2
PIN FUNCTIONS GND (Pins 1, 8, 9, 16):
Power Ground and Signal Ground.
SW (Pin 6):
Switch Pin. Connect the inductor at this pin. Tie to GND plane for best thermal performance. Minimize the trace at this pin to reduce EMI.
OPENLED (Pin 2):
Open LED Status Pin. The OPENLED
ANODE (Pin 7):
Internal Schottky Anode Pin. pin asserts if the FB input is greater than the FB regulation
CATHODE (Pin 10):
Internal Schottky Cathode Pin. threshold minus 60mV (typical). The pin must have an external pull-up resistor to function. When the PWM input
ISP (Pin 11):
Current Sense Resistor Positive Pin. This is low and the converter is idle, the OPENLED condition input is the noninverting input of the internal current sense is latched to the last valid state when the PWM input was amplifi er. Input bias current increases with VISP–VISN high. When the PWM input goes high again, the OPENLED increase. pin will be updated. This pin may be used to report an
ISN (Pin 12):
Current Sense Resistor Negative Pin. This open LED fault. input is the inverting input of the internal current sense
PWM (Pin 3):
Pulse Width Modulated Input. A signal amplifi er. low disables the oscillator and turns off the main switch.
FB (Pin 13):
Voltage Loop Feedback Pin. It is used to PWM has an internal pull-down resistor. Tie PWM pin to connect to output resistor divider for constant voltage VREF if not used. regulation or open LED protection. The internal trans-
SHDN/UVLO (Pin 4):
Shutdown and Undervoltage Lockout conductance amplifi er will regulate FB to 1.22V (nominal) Pin. An accurate 1.22V falling threshold with externally through the DC/DC converter. If the FB input is regulating programmable hysteresis detects when power is okay to the loop, the OPENLED pull-down is asserted. This action enable switching. Rising hysteresis is generated by the may signal an open LED fault. Do not leave the FB pin external resistor divider and an accurate internal 2.2μA open. If not used, connect to GND. pull-down current. Above the 1.25V (nominal) rising
CTRL (Pin 14):
Current Sense Threshold Voltage Adjust- threshold (but below 6V), SHDN/UVLO input bias current ment Pin. This pin sets the threshold voltage across the is sub-μA. Below the falling threshold, a 2.2μA pull-down sense resistor between ISP and ISN. Connect directly to current is enabled so the user can defi ne the hysteresis the VREF pin or a voltage above 1.2V for full-scale thresh- with external resistor selection. Tie to 0.4V or less to dis- old of 250mV, or use a voltage between 0.1V and 1.0V to able device and reduce VIN quiescent current below 1μA. linearly adjust the threshold. A voltage between 1.0V and Pin may be tied to VIN, but do not tie it to a voltage higher 1.2V transitions to the full-scale threshold. Tie CTRL pin than VIN if VIN is less than 6V. to the VREF pin if not used.
VIN (Pin 5):
Input Supply Pin. This pin must be locally
VREF (Pin 15):
Reference Output Pin. Typically 2V. This bypassed with a 1μF ceramic capacitor (or larger) placed pin can supply up to 100μA. close to it. 3519fa 6