Datasheet ATmega162, ATmega162V - Complete (Atmel) - 4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATmega162 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an external memory interface, 35 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, four flexible Timer/Counters with compare modes, internal and external interrupts, two serial programmable USARTs, a pro- grammable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot Pro- gram running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexi- ble and cost effective solution to many embedded control applications. The ATmega162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
ATmega161 and
The ATmega162 is a highly complex microcontroller where the number of I/O locations super-
ATmega162
sedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-ward
Compatibility
compatibility with the ATmega161, all I/O locations present in ATmega161 have the same loca- tions in ATmega162. Some additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega161 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega161 compatibility mode can be selected by programming the fuse M161C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega161. Also, the Extended Inter- rupt Vec-tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can replace the ATmega161 on current Printed Circuit Boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices.
ATmega161
Programming the M161C will change the following functionality:
Compatibility Mode
• The extended I/O map will be configured as internal RAM once the M161C Fuse is programmed.
4 ATmega162/V
2513L–AVR–03/2013 Document Outline Features Pin Configurations Disclaimer Overview Block Diagram ATmega161 and ATmega162 Compatibility ATmega161 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E(PE2..PE0) RESET XTAL1 XTAL2 Resources Data Retention About Code Examples AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y- register, and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATmega162 Memories In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory External Memory Interface Overview Using the External Memory Interface Address Latch Requirements Pull-up and Bus Keeper Timing XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB Using all 64KB Locations of External Memory System Clock and Clock Options Clock Systems and their Distribution CPU clock – clkCPU I/O clock – clkI/O Flash clock – clkFLASH Asynchronous Timer clock – clkASY Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock Clock output buffer Timer/Counter Oscillator System Clock Prescaler Clock Prescale Register – CLKPR Power Management and Sleep Modes MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode Power-save Mode Standby Mode Extended Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins JTAG Interface and On-chip Debug System System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Control and Status Register – MCUCSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control Register – WDTCR Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 Interrupts Interrupt Vectors in ATmega162 Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR I/O-Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected pins Alternate Port Functions Special Function IO Register – SFIOR Alternate Functions of Port A Alternate Functions Of Port B Alternate Functions of Port C Alternate Functions of Port D Alternate Functions of Port E Register Description for I/O- Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE External Interrupts MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR General Interrupt Control Register – GICR General Interrupt Flag Register – GIFR Pin Change Mask Register 1 – PCMSK1 Pin Change Mask Register 0 – PCMSK0 8-bit Timer/Counter0 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers Internal Clock Source Prescaler Reset External Clock Source Special Function IO Register – SFIOR 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) Restriction in ATmega161 Compatibility Mode Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter3 – TCNT3H and TCNT3L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Output Compare Register 3 A – OCR3AH and OCR3AL Output Compare Register 3 B – OCR3BH and OCR3BL Input Capture Register 1 – ICR1H and ICR1L Input Capture Register 3 – ICR3H and ICR3L Timer/Counter Interrupt Mask Register – TIMSK(1) Extended Timer/Counter Interrupt Mask Register – ETIMSK(1) Timer/Counter Interrupt Flag Register – TIFR(1) Extended Timer/Counter Interrupt Flag Register – ETIFR(1) 8-bit Timer/Counter2 with PWM and Asynchronous operation Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Timer/Counter Register – TCNT2 Output Compare Register – OCR2 Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter Prescaler Special Function IO Register – SFIOR Serial Peripheral Interface – SPI SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR Data Modes USART Dual USART AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bit Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM Accessing UBRRH/ UCSRC Registers Write Access Read Access USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA USART Control and Status Register B – UCSRB USART Control and Status Register C – UCSRC(1) USART Baud Rate Registers – UBRRL and UBRRH(1) Examples of Baud Rate Setting Analog Comparator Analog Comparator Control and Status Register – ACSR JTAG Interface and On-chip Debug System Features Overview Test Access Port – TAP TAP Controller Using the Boundary-scan Chain Using the On-chip Debug system On-chip debug specific JTAG instructions PRIVATE0; 0x8 PRIVATE1; 0x9 PRIVATE2; 0xA PRIVATE3; 0xB On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Using the JTAG Programming Capabilities Bibliography IEEE 1149.1 (JTAG) Boundary-scan Features System Overview Data Registers Bypass Register Device Identification Register Reset Register Boundary-scan Chain Boundary-scan Specific JTAG Instructions EXTEST; 0x0 IDCODE; 0x1 SAMPLE_PRELOAD; 0x2 AVR_RESET; 0xC BYPASS; 0xF Boundary-scan Related Register in I/O Memory MCU Control and Status Register – MCUCSR Boundary-scan Chain Scanning the Digital Port Pins Scanning the RESET pin Scanning the Clock Pins Scanning the Analog Comparator ATmega162 Boundary-scan Order Boundary-scan Description Language Files Boot Loader Support – Read- While-Write Self- programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read- While-Write Flash Sections RWW – Read-While- Write Section NRWW – No Read- While-Write Section Boot Loader Lock Bits Entering the Boot Loader Program Store Program Memory Control Register – SPMCR Addressing the Flash During Self- programming Self-programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Using the SPM Interrupt Consideration while Updating BLS Prevent Reading the RWW Section During Self-programming Setting the Boot Loader Lock Bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash When Using SPM Simple Assembly Code Example for a Boot Loader ATmega162 Boot Loader Parameters Memory Programming Program And Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Extended Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading SPI Serial Programming Pin Mapping SPI Serial Programming Algorithm SPI Serial Programming Characteristics Programming via the JTAG Interface Programming Specific JTAG Instructions AVR_RESET (0xC) PROG_ENABLE (0x4) PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) PROG_PAGEREAD (0x7) Data Registers Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register Programming Algorithm Entering Programming Mode Leaving Programming Mode Performing Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuses Programming the Lock Bits Reading the Fuses and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive SPI Timing Characteristics External Data Memory Timing ATmega162 Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Power-save Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 44M1 Errata ATmega162, all rev. Datasheet Revision History Changes from Rev. 2513K-08/07 to Rev. 2513L-03/13 Changes from Rev. 2513J-08/07 to Rev. 2513K-07/09 Changes from Rev. 2513I-04/07 to Rev. 2513J-08/07 Changes from Rev. 2513H-04/06 to Rev. 2513I-04/07 Changes from Rev. 2513G-03/05 to Rev. 2513H-04/06 Changes from Rev. 2513F-09/03 to Rev. 2513G-03/05 Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03 Changes from Rev. 2513C-09/02 to Rev. 2513D-04/03 Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02 Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02 Table of Contents