Datasheet ATmega128, ATmega128L - Complete (Atmel) - 8

ATmega128 Resources
A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: 1.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C
About Code
This datasheet contains simple code examples that briefly show how to use various parts of the
Examples
device. These code examples assume that the part specific header file is included before compi- lation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
Capacitive touch sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan- nels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website.
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2467X–AVR–06/11 Document Outline Features Pin Configurations Overview Block Diagram ATmega103 and ATmega128 Compatibility ATmega103 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) Port G (PG4..PG0) RESET XTAL1 XTAL2 AVCC AREF PEN Resources Data Retention About Code Examples Capacitive touch sensing AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File X-register, Y-register, and Z-register Stack Pointer RAM Page Z Select Register – RAMPZ Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATmega128 Memories In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory External Memory Interface Overview ATmega103 Compatibility Using the External Memory Interface Address Latch Requirements Pull-up and Bus- keeper Timing XMEM Register Description MCU Control Register – MCUCR External Memory Control Register A – XMCRA External Memory Control Register B – XMCRB Using all Locations of External Memory Smaller than 64 Kbyte Using all 64 Kbyte Locations of External Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Asynchronous Timer Clock – clkASY ADC Clock – clkADC XTAL Divide Control Register – XDIV Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock Timer/Counter Oscillator Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode Standby Mode Extended Standby Mode Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins JTAG Interface and On-chip Debug System System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Control and Status Register – MCUCSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control Register – WDTCR Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 Interrupts Interrupt Vectors in ATmega128 Moving Interrupts Between Application and Boot Space MCU Control Register – MCUCR I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected pins Alternate Port Functions Special Function IO Register – SFIOR Alternate Functions of Port A Alternate Functions of Port B Alternate Functions of Port C Alternate Functions of Port D Alternate Functions of Port E Alternate Functions of Port F Alternate Functions of Port G Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE Port F Data Register – PORTF Port F Data Direction Register – DDRF Port F Input Pins Address – PINF Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING External Interrupts External Interrupt Control Register A – EICRA External Interrupt Control Register B – EICRB External Interrupt Mask Register – EIMSK External Interrupt Flag Register – EIFR 8-bit Timer/Counter0 with PWM and Asynchronous Operation Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter0 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter Prescaler Special Function IO Register – SFIOR 16-bit Timer/Counter (Timer/Counter 1 and Timer/Counter3 ) Restrictions in ATmega103 Compatibility Mode Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Pin Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B Timer/Counter1 Control Register C – TCCR1C Timer/Counter3 Control Register C – TCCR3C Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter3 – TCNT3H and TCNT3L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Output Compare Register 1 C – OCR1CH and OCR1CL Output Compare Register 3 A – OCR3AH and OCR3AL Output Compare Register 3 B – OCR3BH and OCR3BL Output Compare Register 3 C – OCR3CH and OCR3CL Input Capture Register 1 – ICR1H and ICR1L Input Capture Register 3 – ICR3H and ICR3L Timer/Counter Interrupt Mask Register – TIMSK Extended Timer/Counter Interrupt Mask Register – ETIMSK Timer/Counter Interrupt Flag Register – TIFR Extended Timer/Counter Interrupt Flag Register – ETIFR Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source Special Function IO Register – SFIOR 8-bit Timer/Counter2 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Timer/Counter Register – TCNT2 Output Compare Register – OCR2 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Output Compare Modulator (OCM1C2) Overview Description Timing Example Serial Peripheral Interface – SPI SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR Data Modes USART Dual USART Overview AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bit Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM USART Register Description USARTn I/O Data Register – UDRn USART Control and Status Register A – UCSRnA USARTn Control and Status Register B – UCSRnB USART Control and Status Register C – UCSRnC USART Baud Rate Registers – UBRRnL and UBRRnH Examples of Baud Rate Setting Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions Address Packet Format Data Packet Format Combining Address and Data Packets Into a Transmission Multi-master Bus Systems, Arbitration and Synchronization Overview of the TWI Module Scl and SDA Pins Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR TWI Status Register – TWSR TWI Data Register – TWDR TWI (Slave) Address Register – TWAR Using the TWI Transmission Modes Master Transmitter Mode Master Receiver Mode Slave Receiver Mode Slave Transmitter Mode Miscellaneous States Combining Several TWI Modes Multi-master Systems and Arbitration Analog Comparator Special Function IO Register – SFIOR Analog Comparator Control and Status Register – ACSR Analog Comparator Multiplexed Input Analog to Digital Converter Features Operation Starting a Conversion Prescaling and Conversion Timing Differential Gain Channels Changing Channel or Reference Selection ADC Input Channels ADC Voltage Reference ADC Noise Canceler Analog Input Circuitry Analog Noise Canceling Techniques Offset Compensation Schemes ADC Accuracy Definitions ADC Conversion Result ADC Multiplexer Selection Register – ADMUX ADC Control and Status Register A – ADCSRA The ADC Data Register – ADCL and ADCH JTAG Interface and On-chip Debug System Features Overview Test Access Port – TAP TAP Controller Using the Boundary-scan Chain Using the On-chip Debug System On-chip Debug Specific JTAG Instructions PRIVATE0; $8 PRIVATE1; $9 PRIVATE2; $A PRIVATE3; $B On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Using the JTAG Programming Capabilities Bibliography IEEE 1149.1 (JTAG) Boundary- scan Features System Overview Data Registers Bypass Register Device Identification Register Reset Register Boundary-scan Chain Boundary-scan Specific JTAG Instructions EXTEST; $0 IDCODE; $1 SAMPLE_PRELOAD; $2 AVR_RESET; $C BYPASS; $F Boundary-scan Related Register in I/O Memory MCU Control and Status Register – MCUCSR Boundary-scan Chain Scanning the Digital Port Pins Boundary-scan and the Two-wire Interface Scanning the RESET Pin Scanning the Clock Pins Scanning the Analog Comparator Scanning the ADC ATmega128 Boundary-scan Order Boundary-scan Description Language Files Boot Loader Support – Read- While-Write Self- Programming Boot Loader Features Application and Boot Loader Flash Sections Application Section Boot Loader Section – BLS Read-While-Write and No Read- While-Write Flash Sections Read-While-Write Section – RWW No Read-While-Write Section – NRWW Boot Loader Lock Bits Entering the Boot Loader Program Store Program Memory Control and Status Register – SPMCSR Addressing the Flash During Self- Programming Self-Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self-Programming Setting the Boot Loader Lock Bits by SPM EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash when Using SPM Simple Assembly Code Example for a Boot Loader ATmega128 Boot Loader Parameters Memory Programming Program and Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Extended Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading SPI Serial Programming Pin Mapping SPI Serial Programming Algorithm Data Polling Flash Data Polling EEPROM SPI Serial Programming Characteristics Programming Via the JTAG Interface Programming Specific JTAG Instructions AVR_RESET ($C) PROG_ENABLE ($4) PROG_COMMANDS ($5) PROG_PAGELOAD ($6) PROG_PAGEREAD ($7) Data Registers Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register Programming Algorithm Entering Programming Mode Leaving Programming Mode Performing Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuses Programming the Lock Bits Reading the Fuses and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Electrical Characteristics Absolute Maximum Ratings* DC Characteristics Speed Grades External Clock Drive Waveforms External Clock Drive Two-wire Serial Interface Characteristics SPI Timing Characteristics ADC Characteristics External Data Memory Timing Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Power-save Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulse width Register Summary Instruction Set Summary Ordering Information Packaging Information 64A 64M1 Errata ATmega128 Rev. F to M Datasheet Revision History Rev. 2467X-06/11 Rev. 2467W-05/11 Rev. 2467V-02/11 Rev. 2467U-08/10 Rev. 2467T-07/10 Rev. 2467S-07/09 Rev. 2467R-06/08 Rev. 2467Q-05/08 Rev. 2467P-08/07 Rev. 2467O-10/06 Rev. 2467N-03/06 Rev. 2467M-11/04 Rev. 2467L-05/04 Rev. 2467K-03/04 Rev. 2467J-12/03 Rev. 2467I-09/03 Rev. 2467H-02/03 Rev. 2467G-09/02 Rev. 2467F-09/02 Rev. 2467E-04/02 Rev. 2467D-03/02 Rev. 2467C-02/02 Table of Contents