Datasheet LTC3839 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Fast, Accurate, 2-Phase, Single-Output Step-Down DC/DC Controller with Differential Output Sensing |
| Seiten / Seite | 50 / 10 — PIN FUNCTIONS PGOOD (Pin 13):. INTV. CC (Pin 21):. BOOST1, BOOST2 (Pin … |
| Dateiformat / Größe | PDF / 944 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS PGOOD (Pin 13):. INTV. CC (Pin 21):. BOOST1, BOOST2 (Pin 14, Pin 27):. EXTV. CC (Pin 22):. TG1, TG2 (Pin 15, Pin 26):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC3839
PIN FUNCTIONS PGOOD (Pin 13):
Power Good Indicator Output. This CDRVCC and the (–) terminal of CIN. Connect the exposed open-drain logic output is pulled to ground when the pad and PGND pin to SGND pin using a single PCB trace output voltage goes out of a ±7.5% window around the under the IC. The exposed pad must be soldered to the regulation point, after a 50µs power-bad-masking delay. circuit board ground for electrical connection and rated Returning to the regulation point, there is a 20µs delay to thermal performance. power good, and a hysteresis of around 2% on both sides
INTV
of the voltage window.
CC (Pin 21):
Supply Input for Internal Circuitry (Not Including Gate Drivers). Normally powered from the DRVCC
BOOST1, BOOST2 (Pin 14, Pin 27):
Boosted Floating pins through a decoupling RC filter to SGND (typically Supplies for Top MOSFET Drivers. The (+) terminal of the 2Ω and 1µF). bootstrap capacitor, CB, connects to this pin. The BOOST
EXTV
pins swing by a V
CC (Pin 22):
External Power Input. When EXTVCC IN between a diode drop below DRVCC, exceeds the switchover voltage (typically 4.6V), an internal or (DRVCC – VD) and (VIN + DRVCC – VD). switch connects this pin to DRVCC2 and shuts down the
TG1, TG2 (Pin 15, Pin 26):
Top Gate Driver Outputs. The internal regulator so that INTVCC and gate drivers draw TG pins drive the gates of the top N-channel power MOSFET power from EXTVCC. The VIN pin still needs to be powered with a voltage swing of VDRVCC between SW and BOOST. up but draws minimum current.
SW1, SW2 (Pin 16, Pin 25):
Switch Node Connection to
RUN (Pin 28):
Run Control Inputs. An internal propor- Inductors. Voltage swings are from a diode voltage below tional-to-absolute-temperature (PTAT) pull-up current ground to VIN. The (–) terminal of the bootstrap capacitor, source (~2.5µA at 25°C) is constantly connected to this CB, connects to this node. pin. Taking the RUN pin below a threshold voltage (~0.8V
BG1, BG2 (Pin 17, Pin 24):
Bottom Gate Driver Outputs. at 25°C) shuts down all bias of INTVCC and DRVCC and The BG pins drive the gates of the bottom N-channel power places the LTC3839 into micropower shutdown mode. MOSFET between PGND and DRV Allowing the RUN pin to rise above this threshold would CC. turn on the internal bias supply and the circuitry. When
DRVCC1, DRVCC2 (Pin 18, Pin 23):
Supplies of Bottom the RUN pin rises above 1.2V, both channels’ TG and BG Gate Drivers. DRVCC1 is also the output of an internal 5.3V drivers are turned on and an additional 10µA temperature- regulator. DRVCC2 is also the output of the EXTVCC switch. independent pull-up current is connected internally to the Normally the two DRVCC pins are shorted together on the RUN pin. The RUN pin can sink up to 100µA, or be forced PCB, and decoupled to PGND with a minimum of 4.7µF no higher than 6V. ceramic capacitor, CDRVCC.
VRNG (Pin 32):
Current Sense Voltage Range Input. When
VIN (Pin 19):
Input Voltage Supply. The supply voltage programmed between 0.6V and 2V, the voltage applied to can range from 4.5V to 38V. For increased noise immunity VRNG is twenty times (20×) the maximum sense voltage decouple this pin to SGND with an RC filter. Voltage at this between SENSE1,2+ and SENSE1,2–, i.e., for either chan- pin is also used to adjust top gate on-time, therefore it nel, (V + – SENSE – VSENSE ) = 0.05 • VRNG. If a VRNG is tied is recommended to tie this pin to the main power input to SGND, the channel operates with a maximum sense supply through an RC filter. voltage of 30mV, equivalent to a VRNG of 0.6V; If tied to
PGND (Pin 20, Exposed Pad Pin 33):
Power Ground. INTVCC, a maximum sense voltage of 50mV, equivalent Connect this pin as close as practical to the source of to a VRNG of 1V. the bottom N-channel power MOSFET, the (–) terminal of 3839fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Typical Performance Characteristics Pin Functions Functional Diagram Operation Typical Applications Typical Application Related Parts
PIN FUNCTIONS PGOOD (Pin 13):
Power Good Indicator Output. This CDRVCC and the (–) terminal of CIN. Connect the exposed open-drain logic output is pulled to ground when the pad and PGND pin to SGND pin using a single PCB trace output voltage goes out of a ±7.5% window around the under the IC. The exposed pad must be soldered to the regulation point, after a 50µs power-bad-masking delay. circuit board ground for electrical connection and rated Returning to the regulation point, there is a 20µs delay to thermal performance. power good, and a hysteresis of around 2% on both sides
INTV
of the voltage window.
CC (Pin 21):
Supply Input for Internal Circuitry (Not Including Gate Drivers). Normally powered from the DRVCC
BOOST1, BOOST2 (Pin 14, Pin 27):
Boosted Floating pins through a decoupling RC filter to SGND (typically Supplies for Top MOSFET Drivers. The (+) terminal of the 2Ω and 1µF). bootstrap capacitor, CB, connects to this pin. The BOOST
EXTV
pins swing by a V
CC (Pin 22):
External Power Input. When EXTVCC IN between a diode drop below DRVCC, exceeds the switchover voltage (typically 4.6V), an internal or (DRVCC – VD) and (VIN + DRVCC – VD). switch connects this pin to DRVCC2 and shuts down the
TG1, TG2 (Pin 15, Pin 26):
Top Gate Driver Outputs. The internal regulator so that INTVCC and gate drivers draw TG pins drive the gates of the top N-channel power MOSFET power from EXTVCC. The VIN pin still needs to be powered with a voltage swing of VDRVCC between SW and BOOST. up but draws minimum current.
SW1, SW2 (Pin 16, Pin 25):
Switch Node Connection to
RUN (Pin 28):
Run Control Inputs. An internal propor- Inductors. Voltage swings are from a diode voltage below tional-to-absolute-temperature (PTAT) pull-up current ground to VIN. The (–) terminal of the bootstrap capacitor, source (~2.5µA at 25°C) is constantly connected to this CB, connects to this node. pin. Taking the RUN pin below a threshold voltage (~0.8V
BG1, BG2 (Pin 17, Pin 24):
Bottom Gate Driver Outputs. at 25°C) shuts down all bias of INTVCC and DRVCC and The BG pins drive the gates of the bottom N-channel power places the LTC3839 into micropower shutdown mode. MOSFET between PGND and DRV Allowing the RUN pin to rise above this threshold would CC. turn on the internal bias supply and the circuitry. When
DRVCC1, DRVCC2 (Pin 18, Pin 23):
Supplies of Bottom the RUN pin rises above 1.2V, both channels’ TG and BG Gate Drivers. DRVCC1 is also the output of an internal 5.3V drivers are turned on and an additional 10µA temperature- regulator. DRVCC2 is also the output of the EXTVCC switch. independent pull-up current is connected internally to the Normally the two DRVCC pins are shorted together on the RUN pin. The RUN pin can sink up to 100µA, or be forced PCB, and decoupled to PGND with a minimum of 4.7µF no higher than 6V. ceramic capacitor, CDRVCC.
VRNG (Pin 32):
Current Sense Voltage Range Input. When
VIN (Pin 19):
Input Voltage Supply. The supply voltage programmed between 0.6V and 2V, the voltage applied to can range from 4.5V to 38V. For increased noise immunity VRNG is twenty times (20×) the maximum sense voltage decouple this pin to SGND with an RC filter. Voltage at this between SENSE1,2+ and SENSE1,2–, i.e., for either chan- pin is also used to adjust top gate on-time, therefore it nel, (V + – SENSE – VSENSE ) = 0.05 • VRNG. If a VRNG is tied is recommended to tie this pin to the main power input to SGND, the channel operates with a maximum sense supply through an RC filter. voltage of 30mV, equivalent to a VRNG of 0.6V; If tied to
PGND (Pin 20, Exposed Pad Pin 33):
Power Ground. INTVCC, a maximum sense voltage of 50mV, equivalent Connect this pin as close as practical to the source of to a VRNG of 1V. the bottom N-channel power MOSFET, the (–) terminal of 3839fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Typical Performance Characteristics Pin Functions Functional Diagram Operation Typical Applications Typical Application Related Parts