Datasheet LTC3834-1 (Analog Devices) - 10

LTC3834-1
U OPERATIO (Refer to Functional Diagram) Light Load Current Operation (Burst Mode Operation,
Mode operation. However, continuous operation has the
Pulse-Skipping, or Continuous Conduction)
advantages of lower output ripple and less interference to
(PLLIN/MODE Pin)
audio circuitry. In forced continuous mode, the output ripple is independent of load current. The LTC3834-1 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skip- When the PLLIN/MODE pin is connected for pulse-skip- ping mode, or forced continuous conduction mode at low ping mode or clocked by an external clock source to use load currents. To select Burst Mode operation, tie the the phase-locked loop (see Frequency Selection and Phase- PLLIN/MODE pin to a DC voltage below 0.8V (e.g., SGND). Locked Loop section), the LTC3834-1 operates in PWM To select forced continuous operation, tie the PLLIN/ pulse-skipping mode at light loads. In this mode, con- MODE pin to INTVCC. To select pulse-skipping mode, tie stant-frequency operation is maintained down to approxi- the PLLIN/MODE pin to a DC voltage greater than 0.8V and mately 1% of designed maximum output current. At very less than INTVCC – 0.5V. light loads, the current comparator ICMP may remain tripped for several cycles and force the external top When the LTC3834-1 is enabled for Burst Mode opera- MOSFET to stay off for the same number of cycles (i.e., tion, the peak current in the inductor is set to approxi- skipping pulses). The inductor current is not allowed to mately one-tenth of the maximum sense voltage even reverse (discontinuous operation). This mode, like forced though the voltage on the ITH pin indicates a lower value. continuous operation, exhibits low output ripple as well as If the average inductor current is lower than the load low audio noise and reduced RF interference as compared current, the error amplifier EA will decrease the voltage on to Burst Mode operation. It provides higher low current the ITH pin. When the ITH voltage drops below 0.4V, the efficiency than forced continuous mode, but not nearly as internal sleep signal goes high (enabling “sleep” mode) high as Burst Mode operation. and both external MOSFETs are turned off. The ITH pin is then disconnected from the output of the EA and “parked”
Frequency Selection and Phase-Locked Loop (PLLLPF
at 0.425V.
and PLLIN/MODE Pins)
In sleep mode, much of the internal circuitry is turned off, The selection of switching frequency is a tradeoff between reducing the quiescent current that the LTC3834-1 draws efficiency and component size. Low frequency operation to only 30μA. In sleep mode, the load current is supplied increases efficiency by reducing MOSFET switching losses, by the output capacitor. As the output voltage decreases, but requires larger inductance and/or capacitance to main- the EA’s output begins to rise. When the output voltage tain low output ripple voltage. drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller The switching frequency of the LTC3834-1’s controllers resumes normal operation by turning on the top external can be selected using the PLLLPF pin. MOSFET on the next cycle of the internal oscillator. If the PLLIN/MODE pin is not being driven by an external When the LTC3834-1 is enabled for Burst Mode operation, clock source, the PLLLPF pin can be floated, tied to the inductor current is not allowed to reverse. The reverse INTVCC, or tied to SGND to select 400kHz, 530kHz, or current comparator (IR) turns off the bottom external 250kHz, respectively. MOSFET just before the inductor current reaches zero, A phase-locked loop (PLL) is available on the LTC3834-1 preventing it from reversing and going negative, thus to synchronize the internal oscillator to an external clock operating in discontinuous operation. source that is connected to the PLLIN/MODE pin. In this In forced continuous operation, the inductor current is case, a series R-C should be connected between the allowed to reverse at light loads or under large transient PLLLPF pin and SGND to serve as the PLL’s loop filter. The conditions. The peak inductor current is determined by the LTC3834-1 phase detector adjusts the voltage on the voltage on the ITH pin, just as in normal operation. In this PLLLPF pin to align the turn-on of the external top MOS- mode, the efficiency at light loads is lower than in Burst FET to the rising edge of the synchronizing signal. 38341f 10