Datasheet LTC3828 (Analog Devices) - 8

LTC3828
PIN FUNCTIONS (SSOP/QFN) SGND (Pin 9/Pin 6):
Small-Signal Ground. Common to
BG2, BG1 (Pins 19, 20/Pins 18, 19):
High Current Gate both controllers, this pin must be routed separately from Drives for Bottom (Synchronous) N-Channel MOSFETs. high current grounds to the common (–) terminals of the Voltage swing at these pins is from ground to INTVCC. COUT capacitors.
PGND (Pin 21/Pin 20):
Driver Power Ground. Connects to
TRCKSS2, TRCKSS1 (Pins 10, 1/Pins 7, 29):
Soft-Start the sources of bottom (synchronous) N-channel MOSFETs, and Output Voltage Tracking Inputs. When one channel is anodes of the Schottky rectifi ers and the (–) terminal(s) confi gured to be the master of two outputs a capacitor to of CIN. ground at this pin sets the ramp rate. The slave channel
DRV
tracks the output of the master channel by reproducing the
CC (Pin 21 QFN Only):
External Power Input to Gate Drives. It can be connected with INTV V CC together and use FB voltage of the master channel with a resistor divider INTV and applying that voltage to its track pin. An internal 1.2μA CC as gate drives power supply. soft-start current is always charging these pins.
INTVCC (Pin 22/Pin 22):
Output of the Internal 5V Linear Low Dropout Regulator. The driver and control circuits are
SENSE2–, SENSE1– (Pins 11, 4/Pins 10, 32):
The (–) powered from this voltage source. Must be decoupled to Input to the Differential Current Comparators. power ground with a minimum of 4.7μF tantalum or other
SENSE2+, SENSE1+ (Pins 12, 3/Pins 11, 31):
The (+) low ESR capacitor. Input to the Differential Current Comparators. The ITH pin
V
voltage and controlled offsets between the SENSE– and
IN (Pin 23/Pin 23):
Main Supply Pin. A bypass capaci- tor should be tied between this pin and the signal ground SENSE+ pins in conjunction with RSENSE set the current pin. trip threshold.
PGOOD (Pin 27/Pin 27):
Open-Drain Logic Output. PGOOD
RUN2, RUN1 (Pins 15, 7/Pins 14, 3):
Run Control Inputs. is pulled to ground when the voltage on either V Forcing RUN pins below 1V would shut down the circuitry OSENSE pin is not within ±7.5% of its set point. required for that particular channel. Forcing the RUN pins over 2V would turn on the IC.
CLKOUT (Pin 28/Pin 28):
Output clock signal available to daisy-chain other controller ICs for additional MOSFET
BOOST2, BOOST1 (Pins 16, 26/Pins 15, 26):
Bootstrapped driver stages/phases. Supplies to the Topside Floating Drivers. Capacitors are connected between the boost and switch pins and
NC (Pins 8, 9 QFN Only):
These “no connect” pins are Schottky diodes are tied between the boost and INTV not tied internally to anything. On the PC layout, these pin CC pins. Voltage swing at the boost pins is from INTV landings should be connected to the SGND plane under CC to (V the IC. IN + INTVCC).
TG2, TG1 (Pins 17, 25/Pins 16, 25):
High Current Gate
Exposed Pad (Pin 33, QFN Only):
Signal Ground. Must Drives for Top N-Channel MOSFETs. These are the outputs be soldered to the PCB, providing a local ground for the of fl oating drivers with a voltage swing equal to INTV control components of the IC, and be tied to the PGND CC – 0.5V superimposed on the switch node voltage SW. pin under the IC.
SW2, SW1 (Pins 18, 24/Pins 17, 24):
Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. 3828fc 8