Datasheet LTC3731H (Analog Devices) - 8

LTC3731H pin FuncTions
BG1 to BG3:
High Current Gate Drives for Bottom N-Channel
PLLFLTR:
The phase-locked loop’s lowpass filter is tied MOSFETs. Voltage swing at these pins is from ground to to this pin. Alternatively, this pin can be driven with an AC VCC. or DC voltage source to vary the frequency of the internal
BOOST1 to BOOST3:
Positive Supply Pins to the Topside oscillator. (Do not apply voltage directly to this pin prior Floating Drivers. Bootstrapped capacitors, charged with to the application of voltage on the VCC pin.) external Schottky diodes and a boost voltage source, are
RUN/SS:
Combination of Soft-Start, Run Control Input connected between the BOOST and SW pins. Voltage swing and Short-Circuit Detection Timer. A capacitor to ground at the BOOST pins is from boost source voltage (typically at this pin sets the ramp time to full current output as well VCC) to this boost source voltage + VIN (where VIN is the as the time delay prior to an output voltage short-circuit external MOSFET supply rail). shutdown. A minimum value of 0.01µF is recommended
CLKOUT:
Output clock signal available to synchronize other on this pin. controller ICs for additional MOSFET stages/phases.
SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–, EAIN:
This is the input to the error amplifier that com-
SENSE3–:
The Inputs to Each Differential Current Com- pares the feedback voltage to the internal 0.6V reference parator. The ITH pin voltage and built-in offsets between voltage. SENSE– and SENSE+ pins, in conjunction with RSENSE, set the current trip threshold level.
FCB:
Forced Continuous Control Input. The voltage ap- plied to this pin sets the operating mode of the controller.
SGND:
Signal Ground. This pin must be routed sepa- The forced continuous current mode is active when the rately under the IC to the PGND pin and then to the main applied voltage is less than 0.6V. Burst Mode operation ground plane. The exposed pad in the UH package must will be active when the pin is allowed to float and a stage be soldered to PCB ground for electrical contact and rated shedding mode will be active if the pin is tied to the V thermal performance. CC pin. (Do not apply voltage directly to this pin prior to the
SW1 to SW3:
Switch Node Connections to Inductors. application of voltage on the VCC pin.) Voltage swing at these pins is from a Schottky diode
PGOOD:
This open-drain output is pulled low when the (external) voltage drop below ground to VIN (where VIN output voltage has been outside the PGOOD tolerance is the external MOSFET supply rail). window for the VPGDLY delay of approximately 100µs.
TG1 to TG3:
High Current Gate Drives for Top N-channel
I
MOSFETs. These are the outputs of floating drivers with
TH:
Error Amplifier Output and Switching Regulator Com- pensation Point. All three current comparator’s thresholds a voltage swing equal to the boost voltage source super- increase with this control voltage. imposed on the switch node voltage SW.
PGND:
Driver Power Ground. This pin connects directly
UVADJ:
Input to the Undervoltage Shutdown Compara- to the sources of the bottom N-channel external MOSFETs tor. When the applied input voltage is less than 1.2V, this and the (–) terminals of C comparator turns off the output MOSFET driver stages IN. and discharges the RUN/SS capacitor.
PHASMD:
This pin determines the phase shift between the first controller’s rising TG signal and the rising edge
VCC:
Main Supply Pin. Because this pin supplies both the of the CLKOUT signal. Logic 0 yields 30 degrees and logic controller circuit power as well as the high power pulses 1 yields 60 degrees. supplied to drive the external MOSFET gates, this pin needs to be very carefully and closely decoupled to the
PLLIN:
Synchronization Input to Phase Detector. This IC’s PGND pin. pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of
VDR:
Supplies power to the bottom gate drivers only. This controller 1 to be synchronized with the rising edge of pin needs to be very carefully and closely decoupled to the PLLIN signal. the IC’s PGND pin. 3731Hfb Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts