Datasheet LTC3525L-3 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 400mA Micropower Synchronous Step-Up DC/DC Converter with Output Disconnect |
| Seiten / Seite | 12 / 5 — PIN FUNCTIONS. SHDN (Pin 1):. VOUT (Pin 4):. GND (Pins 2, 5):. VIN (Pin … |
| Dateiformat / Größe | PDF / 504 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. SHDN (Pin 1):. VOUT (Pin 4):. GND (Pins 2, 5):. VIN (Pin 3):. SW (Pin 6):. BLOCK DIAGRAM
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LTC3525L-3
PIN FUNCTIONS SHDN (Pin 1):
Logic-Controlled Shutdown Input. Connect
VOUT (Pin 4):
Output Voltage Sense and the Output of the to a voltage >0.88V to enable the LTC3525L-3. Connect to Synchronous Rectifier. Connect the output filter capacitor a voltage <0.3V to disable the LTC3525L-3. from VOUT to GND, close to the IC. A minimum value of
GND (Pins 2, 5):
Ground. 10µF ceramic is recommended. Use 22µF for reduced output ripple. The output disconnect feature disconnects
VIN (Pin 3):
Input Voltage. The LTC3525L-3 is powered VOUT from VIN when SHDN is <0.3V. from VIN until VOUT exceeds VIN. Once VOUT is greater than (V
SW (Pin 6):
Switch Pin. Connect an inductor from this IN + 0.2V typical), it is powered from VOUT. Place a ceramic bypass capacitor from V pin to VIN. An internal antiringing resistor is connected IN to GND. A minimum value of 1µF is recommended. across SW and VIN after the inductor current has dropped to zero to minimize EMI.
BLOCK DIAGRAM
VIN 1µF 10µH VIN SW 6 3 VOUT VSEL WELL V SWITCH BEST V VB OUT 4 VOUT 10µF SHDN 1 SHUTDOWN SHUTDOWN GATE DRIVERS AND + ANTI-CROSS CONDUCTION OFFSET – ADJUST V V REF REF – UVLO I UVLO PK + + IPK OFFSET – COMPARATOR ADJUST START-UP LOGIC – IVAL + SHUTDOWN IVALLEY COMPARATOR – FB THERMAL TSD WAKE SHUTDOWN + VREF INTEGRATOR SLEEP COMPARATOR ADJUST 5 2 3525L BD GND GND 3525lfa 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Package Description Revision History Typical Applications Related Parts
PIN FUNCTIONS SHDN (Pin 1):
Logic-Controlled Shutdown Input. Connect
VOUT (Pin 4):
Output Voltage Sense and the Output of the to a voltage >0.88V to enable the LTC3525L-3. Connect to Synchronous Rectifier. Connect the output filter capacitor a voltage <0.3V to disable the LTC3525L-3. from VOUT to GND, close to the IC. A minimum value of
GND (Pins 2, 5):
Ground. 10µF ceramic is recommended. Use 22µF for reduced output ripple. The output disconnect feature disconnects
VIN (Pin 3):
Input Voltage. The LTC3525L-3 is powered VOUT from VIN when SHDN is <0.3V. from VIN until VOUT exceeds VIN. Once VOUT is greater than (V
SW (Pin 6):
Switch Pin. Connect an inductor from this IN + 0.2V typical), it is powered from VOUT. Place a ceramic bypass capacitor from V pin to VIN. An internal antiringing resistor is connected IN to GND. A minimum value of 1µF is recommended. across SW and VIN after the inductor current has dropped to zero to minimize EMI.
BLOCK DIAGRAM
VIN 1µF 10µH VIN SW 6 3 VOUT VSEL WELL V SWITCH BEST V VB OUT 4 VOUT 10µF SHDN 1 SHUTDOWN SHUTDOWN GATE DRIVERS AND + ANTI-CROSS CONDUCTION OFFSET – ADJUST V V REF REF – UVLO I UVLO PK + + IPK OFFSET – COMPARATOR ADJUST START-UP LOGIC – IVAL + SHUTDOWN IVALLEY COMPARATOR – FB THERMAL TSD WAKE SHUTDOWN + VREF INTEGRATOR SLEEP COMPARATOR ADJUST 5 2 3525L BD GND GND 3525lfa 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Package Description Revision History Typical Applications Related Parts