Datasheet LTC3429, LTC3429B (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 600mA, 500kHz Micropower Synchronous Boost Converter with Output Disconnect |
| Seiten / Seite | 12 / 8 — OPERATIO. APPLICATIO S I FOR ATIO. PCB LAYOUT GUIDELINES. Figure 2. … |
| Dateiformat / Größe | PDF / 204 Kb |
| Dokumentensprache | Englisch |
OPERATIO. APPLICATIO S I FOR ATIO. PCB LAYOUT GUIDELINES. Figure 2. Recommended Component Placement. for Single Layer Board
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC3429/LTC3429B
U OPERATIO
is achieved by terminating the switching of the synchro- mode, there will be more power dissipation within the IC. nous PMOS and applying VIN statically on its gate. This This will cause a sharp drop in the efficiency (see Typical ensures that the slope of the inductor current will reverse Performance Characteristics, Efficiency vs VIN). The maxi- during the time current is flowing to the output. Since the mum output current should be limited in order to maintain PMOS no longer acts as a low impedance switch in this an acceptable junction temperature.
U U W U APPLICATIO S I FOR ATIO PCB LAYOUT GUIDELINES
inductor ripple current. Increasing the inductance above The high speed operation of the LTC3429/LTC3429B 10µH will increase size while providing little improvement demands careful attention to board layout. You will not get in output current capability. advertised performance with careless layout. Figure 2 The approximate output current capability of the LTC3429 shows the recommended component placement. A large versus inductance value is given in the equation below and ground pin copper area will help to lower the chip tempera- illustrated graphically in Figure 3. ture. A multilayer board with a separate ground plane is ideal, but not absolutely necessary. ⎛ V • D ⎞ I = η I IN – • 1– D OUT MAX ( ) • ⎜ P ⎟ ( ) ⎝ f • L • 2⎠ where: η = estimated efficiency 1 SW V 6 IN IP = peak current limit value (0.6A) VIN 2 GND V 5 V OUT IN = input (battery) voltage D = steady-state duty ratio = (V 3 FB SHDN 4 SHDN OUT – VIN)/VOUT f = switching frequency (500kHz typical) L = inductance value VOUT 3429 F02 200 VIN = 1.2V RECOMMENDED COMPONENT PLACEMENT. TRACES 180 CARRYING HIGH CURRENT ARE DIRECT. TRACE AREA AT FB PIN IS SMALL. LEAD LENGTH TO BATTERY IS SHORT 160 VOUT = 3.3V 140
Figure 2. Recommended Component Placement
120
for Single Layer Board
100 VOUT = 5V 80
COMPONENT SELECTION
60 OUTPUT CURRENT (mA) 40
Inductor Selection
20 0 The LTC3429/LTC3429B can utilize small surface mount 3 5 7 9 11 13 15 17 19 21 23 and chip inductors due to its fast 500kHz switching INDUCTANCE (µH) 3429 F03 frequency. Typically, a 4.7µH inductor is recommended for most applications. Larger values of inductance will
Figure 3. Maximum Output Current vs
allow greater output current capability by reducing the
Inductance Based on 90% Efficiency
3429fa 8
U OPERATIO
is achieved by terminating the switching of the synchro- mode, there will be more power dissipation within the IC. nous PMOS and applying VIN statically on its gate. This This will cause a sharp drop in the efficiency (see Typical ensures that the slope of the inductor current will reverse Performance Characteristics, Efficiency vs VIN). The maxi- during the time current is flowing to the output. Since the mum output current should be limited in order to maintain PMOS no longer acts as a low impedance switch in this an acceptable junction temperature.
U U W U APPLICATIO S I FOR ATIO PCB LAYOUT GUIDELINES
inductor ripple current. Increasing the inductance above The high speed operation of the LTC3429/LTC3429B 10µH will increase size while providing little improvement demands careful attention to board layout. You will not get in output current capability. advertised performance with careless layout. Figure 2 The approximate output current capability of the LTC3429 shows the recommended component placement. A large versus inductance value is given in the equation below and ground pin copper area will help to lower the chip tempera- illustrated graphically in Figure 3. ture. A multilayer board with a separate ground plane is ideal, but not absolutely necessary. ⎛ V • D ⎞ I = η I IN – • 1– D OUT MAX ( ) • ⎜ P ⎟ ( ) ⎝ f • L • 2⎠ where: η = estimated efficiency 1 SW V 6 IN IP = peak current limit value (0.6A) VIN 2 GND V 5 V OUT IN = input (battery) voltage D = steady-state duty ratio = (V 3 FB SHDN 4 SHDN OUT – VIN)/VOUT f = switching frequency (500kHz typical) L = inductance value VOUT 3429 F02 200 VIN = 1.2V RECOMMENDED COMPONENT PLACEMENT. TRACES 180 CARRYING HIGH CURRENT ARE DIRECT. TRACE AREA AT FB PIN IS SMALL. LEAD LENGTH TO BATTERY IS SHORT 160 VOUT = 3.3V 140
Figure 2. Recommended Component Placement
120
for Single Layer Board
100 VOUT = 5V 80
COMPONENT SELECTION
60 OUTPUT CURRENT (mA) 40
Inductor Selection
20 0 The LTC3429/LTC3429B can utilize small surface mount 3 5 7 9 11 13 15 17 19 21 23 and chip inductors due to its fast 500kHz switching INDUCTANCE (µH) 3429 F03 frequency. Typically, a 4.7µH inductor is recommended for most applications. Larger values of inductance will
Figure 3. Maximum Output Current vs
allow greater output current capability by reducing the
Inductance Based on 90% Efficiency
3429fa 8